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Contents

README

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TPS3838K33QDBVRQ1

Texas Instruments · Supervisor And Reset ICs · SOT-23-5

TPS3838K33QDBVRQ1 from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CT input Timing capacitor input; connect to GND for 10 ms power-on reset delay or to VDD for 200 ms delay.
2 GND power_in Ground; negative power supply reference.
3 MR input Manual reset input (active-low); internal 30 kΩ pull-up resistor to VDD; pull low to assert RESET output.
4 VDD power_in Positive supply voltage input, operating range 1.6 V to 6 V per recommended operating conditions.
5 RESET tri_state Active-low open-drain reset output; asserted (low) when VDD drops below threshold voltage VIT or when MR is pulled low.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

CAD (KiCad official)

  • Symbol: TPS3838K33QDBVRQ1
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps3838k33qdbvrq1-etched.step / tps3838k33qdbvrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3838k33qdbvrq1.step / tps3838k33qdbvrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 9ebef96363b7ef9d, retrieved 2026-10-06, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF