component

TPS3838K33DRVR

Public Made by Adom

by adom

Texas Instruments Supervisor And Reset ICs, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps3838k33drvrfactory-2.0.0extractor-text

Verified TPS3838K33DRVR

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 7 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS3838K33DRVR · WSON-6-EP(2x2) · 7 pins
  • ✓copper: 7 copper pads, none touching another net
  • ✓datasheet: all 7 pin names found in the 33-page datasheet
  • ✓distributor: lcsc C2067219, digikey 296-22631-2-ND, mouser 595-TPS3838K33DRVR
  • ✓family: WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qe4nzxzo/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 7 pins = 7 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 7 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps3838k33drvr.kicad_sym✓ tps3838k33drvr.kicad_mod✓ tps3838k33drvr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17h ago
viewers tps3838k33drvr: viewers · Ray 17h ago
package.json Publish 0.1.0 · Ray 17h ago
page.json Set visibility: public · Ray 17h ago
README.md Publish 0.1.0 · Ray 17h ago
tps3838k33drvr-etched.glb Publish 0.1.0 · Ray 17h ago
tps3838k33drvr-etched.step tps3838k33drvr: factory component page (tier=mfr) · Ray 17h ago
tps3838k33drvr-hero.glb tps3838k33drvr: hero GLB from the etched model (keeps the MPN mark) · Ray 17h ago
tps3838k33drvr-hero.overlay.json Publish 0.1.0 · Ray 17h ago
tps3838k33drvr.glb Publish 0.1.0 · Ray 17h ago
tps3838k33drvr.kicad_mod Publish 0.1.0 · Ray 17h ago
tps3838k33drvr.kicad_sym Publish 0.1.0 · Ray 17h ago
tps3838k33drvr.lbr Publish 0.1.0 · Ray 17h ago
tps3838k33drvr.step Publish 0.1.0 · Ray 17h ago
verification.json Verified: Published by the parts factory: tier mfr, 7 pins · Ray 16h ago

TPS3838K33DRVR

Texas Instruments · Supervisor And Reset ICs · WSON-6-EP(2x2)

TPS3838K33DRVR from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Input supply voltage that the device monitors; recommended supply range is 1.6 V to 6 V.
2 GND power_in Ground reference; all voltage values in the datasheet are referenced to GND.
3 RESET output Active-low open-drain reset output that goes low when VDD falls below VIT or MR is driven low, and releases after reset delay time tD.
4 MR input Manual reset input; driving it to logic low activates RESET, and if unused it should be connected to VDD to minimize current consumption.
5 N/C unconnected No connect; the pin is not connected internally.
6 CT passive Capacitor time delay pin; connect to GND to set a 10 ms reset delay or to VDD to set a 200 ms reset delay.
7 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6-EP(2x2)
Category Power Management (PMIC)
Pins 7

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 7 V Absolute maximum, referenced to GND 4
Voltage on all other pins -0.3 7 V Referenced to GND 4
Maximum low output current IOL 5 mA 4
Maximum high output current IOH -5 mA 4
Input clamp current IIK -10 10 mA VI < 0 or VI > VDD 4
Output clamp current IOK -10 10 mA VO < 0 or VO > VDD 4
Operating temperature TA -40 85 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VDD 1.6 6 V 4
Voltage on CT, MR, RESET pins 0 V Maximum printed as VDD + 0.3 V 4
High-level input voltage VIH 0.7 × VDD Printed as 0.7 × VDD 4
Low-level input voltage VIL 0.3 × VDD Printed as 0.3 × VDD 5
Input transition rise and fall rate at MR Δt/ΔV 100 ns/V 5
Operating temperature TA -40 85 °C 5
Negative-going input threshold voltage VIT 2.84 2.93 2.99 V TPS383xK33, TA = -40°C to 85°C 5
Low-level output voltage RESET VOL 0.4 V TPS3838, VDD = 1.8 V, IOL = 1 mA 5
Power-up reset voltage 0.2 V TPS3838, VDD ≥ 1.1 V, IOL = 50 µA 5
Hysteresis at VDD input VHYS 40 mV 2.5 V < VIT < 3.5 V 5
High-level input current MR IIH -40 -60 -100 µA MR = 0.7 × VDD, VDD = 6 V 5
High-level input current CT IIH -25 25 nA CT = VDD = 6 V 5
Low-level input current MR IIL -130 -200 -340 µA MR = 0 V, VDD = 6 V 6
Low-level input current CT IIL -25 25 nA CT = 0 V, VDD = 6 V 6
High-level output current TPS3838 IOH 25 nA VDD = VIT + 0.2 V, VOH = VDD 6
Supply current IDD 220 400 nA VDD > VIT, VDD < 3 V 6
Supply current IDD 250 450 nA VDD > VIT, VDD > 3 V 6
Supply current IDD 10 15 µA VDD < VIT 6
Internal pullup resistor at MR 30 kΩ 6
Input capacitance at MR and CT CI 5 pF VI = 0 V to VDD 6
Pulse duration at VDD tW 6 µs VIH = VIT + 0.2 V, VIL = VIT, 0.2 V 6
Pulse duration at MR tW 1 µs VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 6
Delay time tD 5 10 15 ms VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = GND 6
Delay time tD 100 200 300 ms VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = VDD 6
Propagation delay time, high-to-low-level output VDD to RESET tPHL 10 µs TPS3838, VIL = VIT, 0.2 V, VIH = VIT + 0.2 V 6
Propagation delay time, high-to-low-level output VDD to RESET tPHL 50 µs TPS3838, VIL = 1.6 V 6
Propagation delay time, high-to-low-level output MR to RESET tPHL 0.3 µs TPS3838, VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 6
Junction-to-ambient thermal resistance RθJA 84.7 °C/W DRV (WSON), 6 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 85.2 °C/W DRV (WSON), 6 pins 5
Junction-to-board thermal resistance RθJB 49.5 °C/W DRV (WSON), 6 pins 5
Junction-to-top characterization parameter ψJT 2.9 °C/W DRV (WSON), 6 pins 5
Junction-to-board characterization parameter ψJB 48.2 °C/W DRV (WSON), 6 pins 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 30 °C/W DRV (WSON), 6 pins 5

CAD (KiCad official)

  • Symbol: TPS3838K33DRVR
  • Footprint: Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm
  • 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: tps3838k33drvr-etched.step / tps3838k33drvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3838k33drvr.step / tps3838k33drvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 6a2b25929a6d0dfb, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF