# TPS3838E18DBVR

**Texas Instruments** · Supervisor And Reset ICs · SOT-23-5

TPS3838E18DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CT | input | Capacitor time delay pin: connect to GND to set the reset delay to 10 ms, or to VDD to set it to 200 ms. |
| 2 | GND | power_in | Ground reference; all voltage ratings in the datasheet are specified with respect to GND. |
| 3 | MR | input | Manual reset input: when driven to logic low, RESET activates; if unused, connect to VDD to minimize current consumption. |
| 4 | RESET | output | Active-low open-drain reset output that goes low when VDD falls below VIT or MR is low, and releases after the reset delay tD once VDD exceeds VIT plus VHYS. |
| 5 | VDD | power_in | Input supply voltage monitored by the device, with a recommended operating range of 1.6 V to 6 V and an absolute maximum of 7 V. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD (recommended) | VDD | 1.6 |  | 6 | V |  | 5 |
| Supply voltage VDD (absolute maximum) | VDD |  |  | 7 | V |  | 4 |
| All other pins voltage |  | -0.3 |  | 7 | V |  | 4 |
| Maximum low output current | IOL |  |  | 5 | mA |  | 4 |
| Maximum high output current | IOH |  |  | -5 | mA |  | 4 |
| Input clamp current | IIK | -10 |  | 10 | mA | VI < 0 or VI > VDD | 4 |
| Output clamp current | IOK | -10 |  | 10 | mA | VO < 0 or VO > VDD | 4 |
| Operating temperature (absolute maximum) | TA | -40 |  | 85 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| Operating temperature (recommended) | TA | -40 |  | 85 | °C |  | 5 |
| Negative-going input threshold voltage (TPS383xE18) | VIT | 1.66 | 1.71 | 1.74 | V | TA = -40°C to 85°C | 5 |
| High-level input current MR | IIH | -40 | -60 | -100 | μA | MR = 0.7 × VDD, VDD = 6 V | 5 |
| High-level input current CT | IIH | -25 |  | 25 | nA | CT = VDD = 6 V | 5 |
| Low-level input current MR | IIL | -130 | -200 | -340 | μA | MR = 0 V, VDD = 6 V | 6 |
| Low-level input current CT | IIL | -25 |  | 25 | nA | CT = 0 V, VDD = 6 V | 6 |
| High-level output current (TPS3838) | IOH |  |  | 25 | nA | VDD = VIT + 0.2 V, VOH = VDD | 6 |
| Low-level output voltage RESET (TPS3836, TPS3838) | VOL |  |  | 0.4 | V | VDD = 1.8 V, IOL = 1 mA | 5 |
| Power-up reset voltage (TPS3838) |  |  |  | 0.2 | V | VDD ≥ 1.1 V, IOL = 50 μA | 5 |
| Supply current (VDD < 3 V) | IDD |  | 220 | 400 | nA | VDD > VIT, VDD < 3 V | 6 |
| Supply current (VDD > 3 V) | IDD |  | 250 | 450 | nA | VDD > VIT, VDD > 3 V | 6 |
| Supply current (VDD below VIT) | IDD |  | 10 | 15 | μA | VDD < VIT | 6 |
| Pulse duration at VDD | tW | 6 |  |  | μs | VIH = VIT + 0.2 V, VIL = VIT, 0.2 V | 6 |
| Pulse duration at MR | tW | 1 |  |  | μs | VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD | 6 |
| Delay time (CT = GND) | tD | 5 | 10 | 15 | ms | VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = GND | 6 |
| Delay time (CT = VDD) | tD | 100 | 200 | 300 | ms | VDD ≥ VIT + 0.2 V, MR = 0.7 × VDD, CT = VDD | 6 |
| Propagation delay high-to-low, VDD to RESET (TPS3836, TPS3838) | tPHL |  | 10 |  | μs | VIL = VIT, 0.2 V, VIH = VIT + 0.2 V | 6 |
| Propagation delay high-to-low, VDD to RESET (TPS3836, TPS3838) | tPHL |  | 50 |  | μs | VIL = 1.6 V | 6 |
| Propagation delay high-to-low, MR to RESET (TPS3836, TPS3838) | tPHL |  | 0.3 |  | μs | VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIL = 0.7 × VDD | 6 |
| Hysteresis at VDD input (1.7 V < VIT < 2.5 V) | VHYS |  | 30 |  | mV | 1.7 V < VIT < 2.5 V | 5 |
| Internal pullup resistor at MR |  |  | 30 |  | kΩ |  | 6 |
| Input capacitance at MR and CT | CI |  | 5 |  | pF | VI = 0 V to VDD | 6 |
| Junction-to-ambient thermal resistance (DBV) | RθJA |  | 153.6 |  | °C/W | DBV (SOT) 5 pins | 5 |
| Junction-to-case (top) thermal resistance (DBV) | RθJC(top) |  | 108.1 |  | °C/W | DBV (SOT) 5 pins | 5 |
| Junction-to-board thermal resistance (DBV) | RθJB |  | 33.5 |  | °C/W | DBV (SOT) 5 pins | 5 |
| Junction-to-top characterization parameter (DBV) | ψJT |  | 10.9 |  | °C/W | DBV (SOT) 5 pins | 5 |
| Junction-to-board characterization parameter (DBV) | ψJB |  | 33.1 |  | °C/W | DBV (SOT) 5 pins | 5 |

## CAD (KiCad official)

- Symbol: `TPS3838E18DBVR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps3838e18dbvr-etched.step` / `tps3838e18dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3838e18dbvr.step` / `tps3838e18dbvr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps3838.pdf) (33 pp, sha256 `6a2b25929a6d0dfb`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps3838e18dbvr-datasheet.pdf)