component

TPS3837L30DBVR

Public Made by Adom

by adom

Texas Instruments Supervisor And Reset ICs, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps3837l30dbvrfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3h ago
viewers tps3837l30dbvr: viewers · Ray 3h ago
package.json Publish 0.1.0 · Ray 3h ago
page.json Set visibility: public · Ray 3h ago
README.md Initial commit: component/tps3837l30dbvr · Ray 3h ago
tps3837l30dbvr-etched.glb tps3837l30dbvr: factory component page (tier=lcsc) · Ray 3h ago
tps3837l30dbvr-etched.step tps3837l30dbvr: factory component page (tier=lcsc) · Ray 3h ago
tps3837l30dbvr-hero.glb Publish 0.1.0 · Ray 3h ago
tps3837l30dbvr-hero.overlay.json Publish 0.1.0 · Ray 3h ago
tps3837l30dbvr.glb Publish 0.1.0 · Ray 3h ago
tps3837l30dbvr.kicad_mod Publish 0.1.0 · Ray 3h ago
tps3837l30dbvr.kicad_sym Publish 0.1.0 · Ray 3h ago
tps3837l30dbvr.lbr Publish 0.1.0 · Ray 3h ago
tps3837l30dbvr.step Publish 0.1.0 · Ray 3h ago

TPS3837L30DBVR

Texas Instruments · Supervisor And Reset ICs · SOT-23-5

TPS3837L30DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CT input Capacitor Time Delay Pin. Connect this pin to GND to set reset delay time to 10 ms. Connect this pin to VDD to set reset delay time to 200 ms.
2 GND power_in Ground
3 MR input Manual Reset. When MR activates to logic low, RESET/RESET activates. When MR is inactive, RESET/RESET depends only on the voltage at VDD. If MR is unused, connect to VDD to minimize current consumption.
4 RESET output Active-High Output Reset. When VDD falls below VIT or when MR activates to logic low, the RESET pin activates to logic high. When VDD rises above VIT plus VHYS and MR deactivates to logic high, RESET deactivates to logic low after reset delay time tD.
5 VDD power_in Input Supply Voltage. This device monitors the voltage at the VDD pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Power Management (PMIC)
Pins 5

CAD (KiCad official)

  • Symbol: TPS3837L30DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: tps3837l30dbvr-etched.step / tps3837l30dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3837l30dbvr.step / tps3837l30dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 6a2b25929a6d0dfb, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF