component
TPS3836J25MDBVTEP
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS3836J25MDBVTEP
Texas Instruments · Supervisor And Reset ICs · SOT-23-5
TPS3836J25MDBVTEP from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CT | input | Delay-time select input: connect to GND for a fixed typical 10 ms reset delay, or to VDD for a typical 200 ms delay; CT input capacitance is 5 pF typical. |
| 2 | GND | power_in | Ground reference for the device; all voltage values in the absolute maximum ratings are specified with respect to GND. |
| 3 | MR | input | Manual reset input with an internal 33 kΩ pullup, requiring VIL of 0.3 × VDD and VIH of 0.7 × VDD; if manual reset is unused, it should be connected to VDD to minimize current consumption. |
| 4 | VDD | power_in | Supply voltage input, recommended 1.6 V to 6 V (absolute maximum 7 V), with a ceramic 0.1 µF bypass capacitor placed near this terminal for best threshold stability. |
| 5 | RESET | output | Active-low push-pull reset output for the TPS3836, asserted while VDD is below VIT or MR is low, with VOL of 0.4 V maximum and VOH of 0.8 × VDD minimum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
CAD (KiCad official)
- Symbol:
TPS3836J25MDBVTEP - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
tps3836j25mdbvtep-etched.step/tps3836j25mdbvtep-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3836j25mdbvtep.step/tps3836j25mdbvtep.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (17 pp, sha256
2e5ccf72753dfadb, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS3836J25MDBVTEP
**Texas Instruments** · Supervisor And Reset ICs · SOT-23-5
TPS3836J25MDBVTEP from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CT | input | Delay-time select input: connect to GND for a fixed typical 10 ms reset delay, or to VDD for a typical 200 ms delay; CT input capacitance is 5 pF typical. |
| 2 | GND | power_in | Ground reference for the device; all voltage values in the absolute maximum ratings are specified with respect to GND. |
| 3 | MR | input | Manual reset input with an internal 33 kΩ pullup, requiring VIL of 0.3 × VDD and VIH of 0.7 × VDD; if manual reset is unused, it should be connected to VDD to minimize current consumption. |
| 4 | VDD | power_in | Supply voltage input, recommended 1.6 V to 6 V (absolute maximum 7 V), with a ceramic 0.1 µF bypass capacitor placed near this terminal for best threshold stability. |
| 5 | RESET | output | Active-low push-pull reset output for the TPS3836, asserted while VDD is below VIT or MR is low, with VOL of 0.4 V maximum and VOH of 0.8 × VDD minimum. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## CAD (KiCad official)
- Symbol: `TPS3836J25MDBVTEP`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `tps3836j25mdbvtep-etched.step` / `tps3836j25mdbvtep-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3836j25mdbvtep.step` / `tps3836j25mdbvtep.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps3837k33-ep) (17 pp, sha256 `2e5ccf72753dfadb`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps3836j25mdbvtep-datasheet.pdf)