component
TPS3808G33QDBVRQ1
Public Made by Adomby adom
Texas Instruments Supervisor and Reset ICs, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
9170557
10d ago
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"package": "SOT-23-6",
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{
"number": "1",
"name": "RESET",
"type": "output",
"description": "Active-low open-drain reset output. Driven low when SENSE drops below VIT (3.07 V typ) or MR is pulled low; released high after the programmed reset delay once SENSE is above VIT and MR is high. Requires a 10 kΩ to 1 MΩ pull-up (may pull to a rail higher than VDD). Max IRESET = 5 mA."
},
{
"number": "2",
"name": "GND",
"type": "power_in",
"description": "Device ground reference."
},
{
"number": "3",
"name": "MR",
"type": "input",
"description": "Active-low manual reset input. Driving this pin low asserts RESET. Internally pulled to VDD through a ~90 kΩ resistor (70 kΩ min), so it may be left floating if unused. VIL ≤ 0.3·VDD, VIH ≥ 0.7·VDD."
},
{
"number": "4",
"name": "CT",
"type": "input",
"description": "Reset-delay programming pin. Leaving open selects the fixed 20 ms delay; tying to VDD via a 40 kΩ resistor selects 300 ms; connecting a ground-referenced capacitor ≥100 pF programs a user delay of 1.25 ms to 10 s. Input capacitance ~5 pF."
},
{
"number": "5",
"name": "SENSE",
"type": "input",
"description": "Voltage-sense input connected to the monitored supply. RESET is asserted when this pin drops below the threshold voltage VIT (3.07 V typical for the G33 option). Very high input impedance; ISENSE ≤ 25 nA. Recommended range 0 V to VDD."
},
{
"number": "6",
"name": "VDD",
"type": "power_in",
"description": "Supply voltage, 1.8 V to 6.5 V (absolute max 7 V). Typical IDD = 2.4 µA at 3.3 V. Bypass with a 0.1 µF ceramic capacitor close to the pin."
}
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"Package": "SOT-23-6",
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"updated_at": "2026-09-25T12:01:24.500Z"
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