component
TPS3808G25DBVR
Public Made by Adomby adom
Texas Instruments Monitors & Reset Circuits, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS3808G25DBVR
Texas Instruments · Monitors & Reset Circuits · SOT-23-6
TPS3808G25DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Open-drain reset output; asserted low when SENSE voltage drops below threshold VIT of 2.33 V or MR pin asserted to logic low; maximum output voltage 0.4 V at IOL = 1 mA with 1.8V ≤ VDD ≤ 6.5V. |
| 2 | GND | power_in | Ground reference connection. |
| 3 | MR | input | Manual reset input; drives RESET output low when asserted to logic low level (0 to 0.3VDD); internally pulled high to VDD with 90 kΩ pull-up resistor; logic high input 0.7VDD to VDD. |
| 4 | CT | input | Reset delay timing capacitor pin; connect via 40-200 kΩ resistor to VDD for 300 ms fixed delay, leave open for 20 ms fixed delay, or connect ≥100 pF capacitor to ground for user-programmable delay 1.25 ms to 10 s. |
| 5 | SENSE | input | Supply voltage sensing input; RESET activated when voltage on this pin drops below threshold VIT of 2.33 V; monitors system voltages from 0.4V to 6.5V; input current 1.7 μA at VSENSE = 6.5 V. |
| 6 | VDD | power_in | Power supply voltage input, 1.7 V to 6.5 V range; place 0.1 µF ceramic bypass capacitor adjacent to pin; quiescent current 2.4 µA typical at VDD = 3.3 V with all pins open. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Supply Chip |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
TPS3808G25DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
tps3808g25dbvr-etched.step/tps3808g25dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3808g25dbvr.step/tps3808g25dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
508cd6b5f24c9f25, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS3808G25DBVR
**Texas Instruments** · Monitors & Reset Circuits · SOT-23-6
TPS3808G25DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Open-drain reset output; asserted low when SENSE voltage drops below threshold VIT of 2.33 V or MR pin asserted to logic low; maximum output voltage 0.4 V at IOL = 1 mA with 1.8V ≤ VDD ≤ 6.5V. |
| 2 | GND | power_in | Ground reference connection. |
| 3 | MR | input | Manual reset input; drives RESET output low when asserted to logic low level (0 to 0.3VDD); internally pulled high to VDD with 90 kΩ pull-up resistor; logic high input 0.7VDD to VDD. |
| 4 | CT | input | Reset delay timing capacitor pin; connect via 40-200 kΩ resistor to VDD for 300 ms fixed delay, leave open for 20 ms fixed delay, or connect ≥100 pF capacitor to ground for user-programmable delay 1.25 ms to 10 s. |
| 5 | SENSE | input | Supply voltage sensing input; RESET activated when voltage on this pin drops below threshold VIT of 2.33 V; monitors system voltages from 0.4V to 6.5V; input current 1.7 μA at VSENSE = 6.5 V. |
| 6 | VDD | power_in | Power supply voltage input, 1.7 V to 6.5 V range; place 0.1 µF ceramic bypass capacitor adjacent to pin; quiescent current 2.4 µA typical at VDD = 3.3 V with all pins open. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Supply Chip |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `TPS3808G25DBVR`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `tps3808g25dbvr-etched.step` / `tps3808g25dbvr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3808g25dbvr.step` / `tps3808g25dbvr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps3808) (40 pp, sha256 `508cd6b5f24c9f25`, retrieved 2026-10-07, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps3808g25dbvr-datasheet.pdf)