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Set visibility: public

Ray ·248083971e ·12d ago ·parent cf5cfbf
1 file changed +8−5
page.json+8−5
@@ -38,7 +38,7 @@         "number": "1",         "name": "RESET",         "type": "tri_state",-        "description": "Open-drain reset output driven to low impedance when SENSE input is below threshold voltage VIT or MR pin is at logic low level, remaining active for user-adjustable delay after SENSE exceeds VIT and MR returns to logic high; requires 10k\u03a9 to 1M\u03a9 pull-up resistor to achieve voltage above VDD."+        "description": "Open-drain reset output driven to low impedance when SENSE input is below threshold voltage VIT or MR pin is at logic low level, remaining active for user-adjustable delay after SENSE exceeds VIT and MR returns to logic high; requires 10kΩ to 1MΩ pull-up resistor to achieve voltage above VDD."       },       {         "number": "2",@@ -50,13 +50,13 @@         "number": "3",         "name": "MR",         "type": "input",-        "description": "Manual reset input pin; driving to logic low level (\u22640.3VDD) forces RESET to become active; internally connected to VDD through 90k\u03a9 pull-up resistor."+        "description": "Manual reset input pin; driving to logic low level (≤0.3VDD) forces RESET to become active; internally connected to VDD through 90kΩ pull-up resistor."       },       {         "number": "4",         "name": "CT",         "type": "input",-        "description": "Reset delay timing programming pin; connect 40k\u03a9 to 200k\u03a9 resistor to VDD for 300ms fixed delay, leave open circuit for 20ms fixed delay, or connect capacitor \u2265100pF to ground for user-programmable delay from 1.25ms to 10s."+        "description": "Reset delay timing programming pin; connect 40kΩ to 200kΩ resistor to VDD for 300ms fixed delay, leave open circuit for 20ms fixed delay, or connect capacitor ≥100pF to ground for user-programmable delay from 1.25ms to 10s."       },       {         "number": "5",@@ -68,7 +68,7 @@         "number": "6",         "name": "VDD",         "type": "power_in",-        "description": "Power supply input voltage in range 1.7V to 6.5V; place 0.1\u00b5F ceramic bypass capacitor near this pin per good analog design practice."+        "description": "Power supply input voltage in range 1.7V to 6.5V; place 0.1µF ceramic bypass capacitor near this pin per good analog design practice."       }     ],     "provenance": {@@ -146,5 +146,8 @@     "docs/tps3808g12dbvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file