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TPS3808G01DBVT
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Texas Instruments Supervisor And Reset ICs, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS3808G01DBVT
Texas Instruments · Supervisor And Reset ICs · SOT-23-6
TPS3808G01DBVT from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | tri_state | RESET is an open-drain output, driven to low-impedance state when RESET is active (SENSE input below threshold voltage VIT or MR pin set to logic low level), and remains at low level during the user-defined reset delay period after SENSE exceeds VIT and MR returns to logic high level. |
| 2 | GND | power_in | Ground reference terminal. |
| 3 | MR | input | Manual reset input; driving MR to logic low (≤0.3VDD) activates RESET; internally connected to VDD through 90kΩ pull-up resistor. |
| 4 | CT | input | Reset delay timing capacitor pin; connect through 40kΩ to 200kΩ resistor to VDD for 300ms delay, leave open for 20ms delay, or connect to ≥100pF grounded capacitor for user-programmable delay from 1.25ms to 10s. |
| 5 | SENSE | input | Voltage sense input pin; RESET becomes active when voltage on this pin falls below threshold voltage VIT. |
| 6 | VDD | power_in | Supply voltage input (1.7V to 6.5V); place 0.1μF ceramic decoupling capacitor near this pin for good analog design practice. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
TPS3808G01DBVT - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
tps3808g01dbvt-etched.step/tps3808g01dbvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3808g01dbvt.step/tps3808g01dbvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
508cd6b5f24c9f25, retrieved 2026-10-06, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS3808G01DBVT
**Texas Instruments** · Supervisor And Reset ICs · SOT-23-6
TPS3808G01DBVT from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | tri_state | RESET is an open-drain output, driven to low-impedance state when RESET is active (SENSE input below threshold voltage VIT or MR pin set to logic low level), and remains at low level during the user-defined reset delay period after SENSE exceeds VIT and MR returns to logic high level. |
| 2 | GND | power_in | Ground reference terminal. |
| 3 | MR | input | Manual reset input; driving MR to logic low (≤0.3VDD) activates RESET; internally connected to VDD through 90kΩ pull-up resistor. |
| 4 | CT | input | Reset delay timing capacitor pin; connect through 40kΩ to 200kΩ resistor to VDD for 300ms delay, leave open for 20ms delay, or connect to ≥100pF grounded capacitor for user-programmable delay from 1.25ms to 10s. |
| 5 | SENSE | input | Voltage sense input pin; RESET becomes active when voltage on this pin falls below threshold voltage VIT. |
| 6 | VDD | power_in | Supply voltage input (1.7V to 6.5V); place 0.1μF ceramic decoupling capacitor near this pin for good analog design practice. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `TPS3808G01DBVT`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `tps3808g01dbvt-etched.step` / `tps3808g01dbvt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3808g01dbvt.step` / `tps3808g01dbvt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps3808) (40 pp, sha256 `508cd6b5f24c9f25`, retrieved 2026-10-06, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps3808g01dbvt-datasheet.pdf)