component

TPS3711DDCT

Public Made by Adom

by adom

Texas Instruments Monitors & Reset Circuits, TSOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chiptps3711ddctfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 3d ago
viewers tps3711ddct: viewers · Ray 3d ago
package.json Publish 0.1.0 · Ray 3d ago
page.json Set visibility: public · Ray 3d ago
README.md Publish 0.1.0 · Ray 3d ago
tps3711ddct-etched.glb Publish 0.1.0 · Ray 3d ago
tps3711ddct-etched.step tps3711ddct: factory component page (tier=lcsc) · Ray 3d ago
tps3711ddct-hero.glb tps3711ddct: hero GLB from the etched model (keeps the MPN mark) · Ray 3d ago
tps3711ddct-hero.overlay.json Publish 0.1.0 · Ray 3d ago
tps3711ddct.glb Publish 0.1.0 · Ray 3d ago
tps3711ddct.kicad_mod Publish 0.1.0 · Ray 3d ago
tps3711ddct.kicad_sym Publish 0.1.0 · Ray 3d ago
tps3711ddct.lbr Publish 0.1.0 · Ray 3d ago
tps3711ddct.step Publish 0.1.0 · Ray 3d ago

TPS3711DDCT

Texas Instruments · Monitors & Reset Circuits · TSOT-23-6

TPS3711DDCT from Texas Instruments, in a TSOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT output Open-drain comparator output that is driven low when SENSE falls below VIT- and goes high impedance when SENSE rises above VIT+; can be pulled up to 25 V and sink up to 10 mA.
2 GND power_in Ground; all three GND pins (2, 4, 6) must be connected to ground.
3 SENSE input Comparator input connected to the monitored voltage through an external resistor divider; OUT is driven low when it drops below VIT- (400 mV typ), with a 0 to 6.5 V operating range.
4 GND power_in Ground; all three GND pins (2, 4, 6) must be connected to ground.
5 VDD power_in Supply-voltage input for a 1.8 V to 36 V supply, with a 0.1 µF ceramic capacitor placed close to the pin.
6 GND power_in Ground; all three GND pins (2, 4, 6) must be connected to ground.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSOT-23-6
Category Power Supply Chip
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply pin voltage VDD 1.8 36 V 4
Input pin voltage VSENSE 0 6.5 V 4
Output pin voltage VOUT 0 25 V 4
Pullup voltage VPULLUP 0 25 V 4
Output pin current IOUT 0 10 mA 4
Junction temperature TJ -40 25 125 °C 4
Abs max VDD VDD -0.3 40 V 4
Abs max VOUT VOUT -0.3 28 V 4
Abs max VSENSE VSENSE -0.3 7 V 4
Abs max output pin current 40 mA 4
Abs max operating junction temperature TJ -40 125 °C 4
Abs max storage temperature Tstg -55 125 °C 4
Junction-to-ambient thermal resistance RθJA 201.6 °C/W DDC (SOT), 6 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 47.8 °C/W 4
Junction-to-board thermal resistance RθJB 51.2 °C/W 4
Power-on reset voltage V(POR) 0.8 V VOL ≤ 0.2 V 5
SENSE negative input threshold voltage VIT- 397 400 403 mV VDD = 1.8 V to 36 V 5
SENSE positive input threshold voltage VIT+ 400 405.5 413 mV VDD = 1.8 V to 36 V 5
SENSE hysteresis voltage VHYS 2 5.5 12 mV HYS = VIT+, VIT- 5
Low-level output voltage VOL 130 250 mV VDD = 1.8 V, IOUT = 3 mA 5
Low-level output voltage VOL 150 250 mV VDD = 5 V, IOUT = 5 mA 5
Input current (SENSE) IIN -25 1 25 nA VDD = 1.8 V and 36 V, VSENSE = 6.5 V 5
Input current (SENSE) IIN -15 1 15 nA VDD = 1.8 V and 36 V, VSENSE = 0.1 V 5
Open-drain leakage current ID(leak) 10 300 nA VDD = 1.8 V and 36 V, VOUT = 25 V 5
Supply current IDD 8 11 µA VDD = 1.8 V, 36 V 5
Undervoltage lockout UVLO 1.3 1.5 1.7 V VDD falling 5
High-to-low propagation delay tpd(HL) 9.9 µs VDD = 24 V, ±10-mV input overdrive, RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV 6
Low-to-high propagation delay tpd(LH) 28.1 µs VDD = 24 V, ±10-mV input overdrive, RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV 6
Startup delay td(start) 155 µs VDD = 5 V 6
Output rise time tr 2.7 µs VDD = 12 V, 10-mV input overdrive, RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD 6
Output fall time tf 0.12 µs VDD = 12 V, 10-mV input overdrive, RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD 6

CAD (KiCad official)

  • Symbol: TPS3711DDCT
  • Footprint: Package_TO_SOT_SMD:TSOT-23-6
  • 3D model: TSOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: tps3711ddct-etched.step / tps3711ddct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3711ddct.step / tps3711ddct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (24 pp, sha256 5675f26ad97454b5, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF