component
TPS3705-50DR
Public Made by Adomby adom
Texas Instruments Supervisor and Reset ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS3705-50DR
Texas Instruments · Supervisor and Reset ICs · SOIC-8
TPS3705-50DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Manual reset input, active low. Driving MR below 0.3xVDD forces RESET active. Internally pulled such that IIH ~ -130 uA and IIL ~ -430 uA at VDD = 6 V; leave open or tie to VDD if unused. |
| 2 | VDD | power_in | Supply voltage input. Recommended operating range 2 V to 6 V (absolute max 7 V). Monitored against the fixed 4.55 V (typ) negative-going threshold VIT-. A 0.1 uF ceramic bypass capacitor is recommended near the pin. |
| 3 | GND | power_in | Ground reference for the device. All voltages are referenced to GND. |
| 4 | PFI | input | Power-fail comparator input. Compared against an internal 1.25 V (typ) reference; when PFI falls below the reference, PFO drives low. High-impedance input ( |
| 5 | PFO | output | Power-fail comparator output, active low (bar over PFO). Drives low when PFI is below the 1.25 V internal reference. Push-pull CMOS output; propagation delay ~1 us typical. |
| 6 | WDI | input | Watchdog timer input. Must be toggled by the processor at least once every t_t(out) (1.6 s typ, 2.3 s max) window; if not toggled, WDO asserts low. Tie to VDD or GND to disable the watchdog (in which case WDO stays high). |
| 7 | RESET | output | Active-low reset output (bar over RESET). Asserted low while VDD < VIT- (4.55 V typ) and held low for the reset delay td (200 ms typ) after VDD returns above VIT+. Also driven low by MR. Valid down to VDD >= 1.1 V. |
| 8 | WDO | output | Watchdog timer output, active low (bar over WDO). Drives low if WDI is not toggled within the watchdog timeout window (1.6 s typ). Push-pull CMOS output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
TPS3705-50DRTPS3705-50DGNTPS3705-50DGNR
CAD (KiCad official)
- Symbol:
TPS3705-50DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps3705-50dr-etched.step/tps3705-50dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3705-50dr.step/tps3705-50dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
364e575055c9d2f1, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).