component

TPS3705-30DR

Public Made by Adom

by adom

Texas Instruments Supervisor And Reset ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps3705-30drfactory-2.0.0extractor-text

Verified TPS3705-30DR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS3705-30DR · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 37-page datasheet
  • ✓distributor: lcsc C702151, digikey 296-29076-2-ND, mouser 595-TPS3705-30DR
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-lytq362e/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps3705-30dr.kicad_sym✓ tps3705-30dr.kicad_mod✓ tps3705-30dr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2h ago
viewers tps3705-30dr: viewers · Ray 2h ago
package.json Publish 0.1.0 · Ray 2h ago
page.json Set visibility: public · Ray 2h ago
README.md Publish 0.1.0 · Ray 2h ago
tps3705-30dr-etched.glb Publish 0.1.0 · Ray 2h ago
tps3705-30dr-etched.step tps3705-30dr: factory component page (tier=mfr) · Ray 2h ago
tps3705-30dr-hero.glb tps3705-30dr: hero GLB from the etched model (keeps the MPN mark) · Ray 2h ago
tps3705-30dr-hero.overlay.json Publish 0.1.0 · Ray 2h ago
tps3705-30dr.glb Publish 0.1.0 · Ray 2h ago
tps3705-30dr.kicad_mod Publish 0.1.0 · Ray 2h ago
tps3705-30dr.kicad_sym Publish 0.1.0 · Ray 2h ago
tps3705-30dr.lbr Publish 0.1.0 · Ray 2h ago
tps3705-30dr.step Publish 0.1.0 · Ray 2h ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 2h ago

TPS3705-30DR

Texas Instruments · Supervisor And Reset ICs · SOIC-8

TPS3705-30DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Manual reset input; the datasheet gives a rise and fall rate limit of 100 ns/V at MR or WDI.
2 VDD power_in Supply voltage pin; the recommended operating range is 2 V to 6 V and the absolute maximum is 7 V.
3 GND power_in Ground reference for all voltages, which are specified with respect to GND.
4 PFI input Power-fail comparator input, with a voltage range of -0.3 V to VDD + 0.3 V.
5 PFO output Power-fail comparator output for power-fail or low-battery warning.
6 WDI input Watchdog timer input (TPS3705-xx only); the rise and fall rate limit is 100 ns/V.
7 RESET output Active-low reset output, asserted while VDD is below the threshold VIT+ and driven low when VDD drops below VIT-.
8 WDO output Watchdog timer output (TPS3705-xx only).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 7 V 5
All other pins voltage range -0.3 7 V All voltage values with respect to GND 5
PFI voltage range VPFI -0.3 V Maximum printed as VDD + 0.3 V 5
Maximum low output current IOL 5 mA 5
Maximum high output current IOH -5 mA 5
Input clamp current IIK -20 20 mA VI < 0 or VI > VDD 5
Output clamp current IOK -20 20 mA VO < 0 or VO > VDD 5
Soldering temperature 260 °C 5
Operating temperature TA -40 85 °C Free-air; TPS3705-33 only has 125 °C, not applicable 5
Storage temperature Tstg -65 150 °C 5
Supply voltage VDD 2 6 V 5
Input voltage VI 0 V Maximum printed as VDD + 0.3 V 5
Input transition rise and fall rate at MR or WDI Δt/ΔV 100 ns/V 5
Operating free-air temperature TA -40 85 °C 5
High-level output voltage VOH 0.8 V VDD = 1.1 V, IOH = -4 µA 7
Low-level output voltage VOL 0.3 V VDD = VIT+ + 0.2 V, IOL = 1 mA 7
Low-level output voltage VOL 0.4 V VDD = 6 V, IOL = 3 mA 7
Power-up reset voltage 0.3 V VDD ≥ 1.1 V, IOL = 50 µA 7
Negative-going input threshold voltage VIT- 2.57 2.63 2.68 V TPS370x-30, TA = 0 °C to 85 °C 7
Negative-going input threshold voltage VIT- 2.57 2.63 2.7 V TPS370x-30, TA = -40 °C to 85 °C 7
Negative-going input threshold voltage, PFI VIT- 1.2 1.25 1.3 V TPS370x-xx, VDD ≥ 2 V, TA = -40 °C to 85 °C 7
Hysteresis, VDD Vhys 50 mV TPS370x-30 7
Hysteresis, PFI Vhys 10 mV TPS370x-xx 7
Average high-level input current, WDI IIH(AV) 100 150 µA WDI = VDD = 6 V, time average (dc = 88%) 7
Average low-level input current, WDI IIL(AV) -20 -15 µA WDI = 0 V, VDD = 6 V, time average (dc = 12%) 7
High-level input current, WDI IIH 120 170 µA WDI = VDD = 6 V 7
High-level input current, MR IIH -180 -130 µA MR = 0.7 × VDD, VDD = 6 V 7
Low-level input current, WDI IIL -170 -120 µA WDI = 0 V, VDD = 6 V 7
Low-level input current, MR IIL -600 -430 µA MR = 0 V, VDD = 6 V 7
Input current, PFI II -1 0 1 µA VDD = 6 V, 0 V ≤ VI ≤ VDD 7
Supply current, TPS3705-xx IDD 30 50 µA VDD = 2 V to 6 V, MR = VDD, MR, WDI and outputs unconnected 7
Input capacitance Ci 5 pF VI = 0 V to VDD 7
Pulse width at VDD tw 6 µs VDD = VIT+ + 0.2 V, VDD = VIT- - 0.2 V 8
Pulse width at MR and WDI tw 100 ns VDD ≥ VIT+ + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 8
Watchdog time out tt(out) 1.1 1.6 2.3 s VDD ≥ VIT+ + 0.2 V, see Figure 7-1 9
Delay time td 140 200 280 ms VDD ≥ VIT+ + 0.2 V, see Figure 7-1 9
Propagation delay time, high-to-low, MR to RESET tPHL 50 250 ns VDD ≥ VIT+ + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 9
Propagation delay time, high-to-low, VDD to RESET tPHL 3 5 µs 9
Propagation delay time, high-to-low, PFI to PFO tPHL 0.5 1 µs VDD = 2 V to 6 V 9
Propagation delay time, low-to-high, PFI to PFO tPLH 0.5 1 µs VDD = 2 V to 6 V 9
Thermal resistance junction-to-ambient, D (SOIC) RθJA 118.2 °C/W Junction-to-ambient, D (SOIC) 8 pins 6
Thermal resistance junction-to-case (top), D (SOIC) RθJC(top) 64.4 °C/W Junction-to-case (top), D (SOIC) 8 pins 6
Thermal resistance junction-to-board, D (SOIC) RθJB 58.5 °C/W Junction-to-board, D (SOIC) 8 pins 6
Junction-to-top characterization parameter, D (SOIC) ψJT 15.8 °C/W Junction-to-top, D (SOIC) 8 pins 6
Junction-to-board characterization parameter, D (SOIC) ψJB 57.9 °C/W Junction-to-board, D (SOIC) 8 pins 6

CAD (KiCad official)

  • Symbol: TPS3705-30DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tps3705-30dr-etched.step / tps3705-30dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3705-30dr.step / tps3705-30dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 cc00684613b09304, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF