TPS3703A7330DSER from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SENSE	input	Input for the monitored supply voltage rail; when SENSE goes above the overvoltage threshold or below the undervoltage threshold, RESET is driven low, and it should connect to VDD when monitoring VDD.
2	VDD	power_in	Supply voltage input pin, with a 0.1-µF ceramic capacitor recommended close to this pin.
3	CT	input	Capacitor time delay pin: connecting it to VDD or leaving it floating selects one of two fixed time delays, and an external capacitor to ground programs the delay.
4	RESET	output	Active-low, open-drain output that goes low when SENSE is above VIT+ (OV) or below VIT- (UV), and requires a pull-up resistor to the desired pull-up voltage.
5	GND	power_in	Ground reference pin.
6	MR	input	Manual reset input: pulling it to a logic low (VMR_L) asserts a reset, the output goes high after the reset delay time (tD) expires once MR is released, and MR can be left floating when not in use.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WSON-6(1.5x1.5)
Category	Power Management (PMIC)
Pins	6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Window threshold tolerance (OV/UV)		-7		7	%	Decoded from MPN digit 7: UV/OV = 7% from nominal threshold	28
Positive-going threshold accuracy (OV)	VIT+(OV)	-0.7	0.25	0.7	%		6
Negative-going threshold accuracy (UV)	VIT-(UV)	-0.7	0.25	0.7	%		6
Hysteresis voltage	VHYS	0.3	0.55	0.8	%	Hysteresis is with respect of the tripoint (VIT-(UV), VIT+(OV))	6
Supply voltage	VDD	1.7		5.5	V		6
Undervoltage lockout	UVLO		1.2	1.7	V	VDD falling below 1.7 V	6
Power on reset voltage	VPOR			1	V	VOL(max) = 0.25 V, IOUT = 15 µA	6
Supply current	IDD		4.5	7	µA	VDD ≤ 5.5 V	6
Input current, SENSE pin	ISENSE		1	1.5	µA	VSENSE = 5 V	6
Low level output voltage	VOL			250	mV	VDD = 1.7 V, IOUT = 0.4 mA	6
Open drain output leakage current	ILKG			300	nA	VDD = VRESET = 5.5 V	6
MR logic low input	VMR_L			0.3	V		6
MR logic high input	VMR_H	1.4			V		6
High level CT pin voltage	VCT_H	1.4			V		6
Manual reset internal pullup resistance	RMR		100		KΩ		6
CT pin charge current	ICT	337	375	413	nA		6
CT pin comparator threshold voltage	VCT	1.133	1.15	1.167	V		6
Reset time delay, TPS3703A	tD	7	10	13	ms	CT = Open	7
Reset time delay, TPS3703A	tD	140	200	260	ms	CT = 10 kΩ to VDD	7
Propagation detect delay	tPD		15	30	µs	Measured from threshold trip point to RESET VOL	7
Output rise time	tR			2.2	µs		7
Output fall time	tF			0.2	µs		7
Startup delay	tSD			300	µs		7
Glitch immunity undervoltage	tGI (VIT-)			3.5	µs	VIT-(UV), 5% Overdrive	7
Glitch immunity overvoltage	tGI (VIT+)			3.5	µs	VIT+(OV), 5% Overdrive	7
Glitch immunity MR pin	tGI (MR)			25	ns		7
Propagation delay from MR low to assert RESET	tPD (MR)			500	ns		7
MR pin pulse width duration to assert RESET	tMR_W			1	µs		7
Voltage VDD	VDD	-0.3		6	V		5
Voltage VRESET	VRESET	-0.3		6	V		5
Voltage VCT	VCT	-0.3		6	V		5
Voltage VSENSE	VSENSE	-0.3		6	V		5
Voltage VMR	VMR	-0.3		6	V		5
Current IRESET	IRESET	-40		40	mA		5
Operating junction temperature	TJ	-40		150	°C		5
Operating free-air temperature	TA	-40		150	°C		5
Storage temperature	Tstg	-65		150	°C		5
Supply pin voltage	VDD	1.7		5.5	V		5
Input pin voltage	VSENSE	0		5.5	V		5
Output pin voltage	VRESET	0		5.5	V		5
Output pin current	IRESET	0.3		10	mA		5
Junction temperature (free-air temperature)	TJ	-40		125	℃		5
Junction-to-ambient thermal resistance	RθJA		184.2		°C/W	DSE (WSON) package	6
Junction-to-case (top) thermal resistance	RθJC(top)		30.6		°C/W	DSE (WSON) package	6
Junction-to-board thermal resistance	RθJB		86.4		°C/W	DSE (WSON) package	6
Junction-to-top characterization parameter	ΨJT		13.4		°C/W	DSE (WSON) package	6
Junction-to-board characterization parameter	ΨJB		86.1		°C/W	DSE (WSON) package	6

CAD (KiCad official)

Symbol: TPS3703A7330DSER
Footprint: Package_SON:WSON-6_1.5x1.5mm_P0.5mm
3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
3D model files: tps3703a7330dser-etched.step / tps3703a7330dser-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3703a7330dser.step / tps3703a7330dser.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (40 pp, sha256 cc65714774e50c97, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS3703A7330DSER

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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