component
TPS3703A7125DSERQ1
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, WSON-6(1.5x1.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS3703A7125DSERQ1
Texas Instruments · Supervisor And Reset ICs · WSON-6(1.5x1.5)
TPS3703A7125DSERQ1 from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE | input | Input for the monitored supply voltage rail; RESET is driven low when SENSE rises above the overvoltage threshold or falls below the undervoltage threshold, and it should be connected to VDD when monitoring the VDD supply. |
| 2 | VDD | power_in | Supply voltage input pin, and good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin. |
| 3 | CT | input | Capacitor time delay pin that selects one of two fixed reset delays when tied to VDD or left floating, or sets a programmable delay when an external capacitor is connected to ground. |
| 4 | RESET | output | Active-low open-drain output that goes low when SENSE rises above the overvoltage threshold (VIT+) or falls below the undervoltage threshold (VIT-), and it must be connected to a pull-up resistor terminated to the desired pull-up voltage. |
| 5 | GND | power_in | Ground connection for the device. |
| 6 | MR | input | Manual reset input that asserts a reset when pulled to a logic low (VMR_L), with RESET going high after the reset delay time (tD) expires once MR is deasserted, and it can be left floating when not in use. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(1.5x1.5) |
| Category | Power Management (PMIC) |
| Pins | 6 |
CAD (KiCad official)
- Symbol:
TPS3703A7125DSERQ1 - Footprint:
Package_SON:WSON-6_1.5x1.5mm_P0.5mm - 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files:
tps3703a7125dserq1-etched.step/tps3703a7125dserq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3703a7125dserq1.step/tps3703a7125dserq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (40 pp, sha256
05a6581745cb5982, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS3703A7125DSERQ1
**Texas Instruments** · Supervisor And Reset ICs · WSON-6(1.5x1.5)
TPS3703A7125DSERQ1 from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE | input | Input for the monitored supply voltage rail; RESET is driven low when SENSE rises above the overvoltage threshold or falls below the undervoltage threshold, and it should be connected to VDD when monitoring the VDD supply. |
| 2 | VDD | power_in | Supply voltage input pin, and good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin. |
| 3 | CT | input | Capacitor time delay pin that selects one of two fixed reset delays when tied to VDD or left floating, or sets a programmable delay when an external capacitor is connected to ground. |
| 4 | RESET | output | Active-low open-drain output that goes low when SENSE rises above the overvoltage threshold (VIT+) or falls below the undervoltage threshold (VIT-), and it must be connected to a pull-up resistor terminated to the desired pull-up voltage. |
| 5 | GND | power_in | Ground connection for the device. |
| 6 | MR | input | Manual reset input that asserts a reset when pulled to a logic low (VMR_L), with RESET going high after the reset delay time (tD) expires once MR is deasserted, and it can be left floating when not in use. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6(1.5x1.5) |
| Category | Power Management (PMIC) |
| Pins | 6 |
## CAD (KiCad official)
- Symbol: `TPS3703A7125DSERQ1`
- Footprint: `Package_SON:WSON-6_1.5x1.5mm_P0.5mm`
- 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
- 3D model files: `tps3703a7125dserq1-etched.step` / `tps3703a7125dserq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps3703a7125dserq1.step` / `tps3703a7125dserq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps3703-q1) (40 pp, sha256 `05a6581745cb5982`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps3703a7125dserq1-datasheet.pdf)