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TPS3703A4120DSERQ1

Texas Instruments · Supervisor And Reset ICs · WSON-6(1.5x1.5)

TPS3703A4120DSERQ1 from Texas Instruments, in a WSON-6(1.5x1.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSE input Input for the monitored supply voltage rail; RESET is driven low when SENSE rises above the overvoltage threshold or falls below the undervoltage threshold, and it should be connected to VDD when VDD itself is monitored.
2 VDD power_in Supply voltage input with a recommended range of 1.7 V to 5.5 V, and a 0.1-µF ceramic capacitor should be placed close to this pin.
3 CT input Capacitor time delay pin that selects one of two fixed reset delays when tied to VDD (with a 10 kΩ pull-up) or left floating, and sets a programmable delay when an external capacitor is connected to ground.
4 RESET output Active-low, open-drain output that goes low when SENSE is above VIT+(OV) or below VIT-(UV) and requires a pull-up resistor to the desired pull-up voltage.
5 GND power_in Ground reference pin for the device.
6 MR input Manual reset input; pulling it to a logic low (VMR_L) asserts RESET, and it can be left floating when not in use because it is internally pulled up to VDD.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-6(1.5x1.5)
Category Power Management (PMIC)
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 1.7 5.5 V 6
Supply current IDD 4.5 7 µA VDD ≤ 5.5 V 6
Positive-going threshold accuracy VIT+(OV) -0.7 0.25 0.7 % 6
Negative-going threshold accuracy VIT-(UV) -0.7 0.25 0.7 % 6
Window threshold tolerance (UV/OV) -4 4 % Tolerance code 4: OV +4%, UV -4% from nominal 1.20 V 27
Nominal monitor threshold voltage 1.2 V Nominal threshold option 120 (1.20 V) 28
Hysteresis voltage VHYS 0.3 0.55 0.8 % 6
Undervoltage lockout UVLO 1.2 1.7 V VDD falling below 1.7 V 6
Power on reset voltage VPOR 1 V VOL(max) = 0.25 V, IOUT = 15 µA 6
Input current, SENSE pin ISENSE 1 1.5 µA VSENSE = 5 V 6
Low level output voltage VOL 250 mV VDD = 1.7 V, IOUT = 0.4 mA 6
Open drain output leakage current ILKG 300 nA VDD = VRESET = 5.5 V 6
MR logic low input VMR_L 0.3 V 6
MR logic high input VMR_H 1.4 V 6
High level CT pin voltage VCT_H 1.4 V 6
Manual reset internal pullup resistance RMR 100 KΩ 6
CT pin charge current ICT 337 375 413 nA 6
CT pin comparator threshold voltage VCT 1.133 1.15 1.167 V 6
Reset time delay, TPS3703A CT = Open tD 7 10 13 ms CT = Open 7
Reset time delay, TPS3703A CT = 10 kΩ to VDD tD 140 200 260 ms CT = 10 kΩ to VDD 7
Propagation detect delay tPD 15 30 µs 7
Output rise time tR 2.2 µs 7
Output fall time tF 0.2 µs 7
Startup delay tSD 300 µs 7
Glitch immunity undervoltage tGI (VIT-) 3.5 µs VIT-(UV), 5% Overdrive 7
Glitch immunity overvoltage tGI (VIT+) 3.5 µs VIT+(OV), 5% Overdrive 7
Glitch immunity MR pin tGI (MR) 25 ns 7
Propagation delay from MR low to assert RESET tPD (MR) 500 ns 7
MR pin pulse width duration to assert RESET tMR_W 1 µs 7
Reset time delay, TPS3703A CT = Open (timing requirement) tD 7 10 13 ms CT = Open 7
Supply pin voltage VDD 1.7 5.5 V 5
Input pin voltage VSENSE 0 5.5 V 5
Output pin voltage VRESET 0 5.5 V 5
MR pin voltage VMR 0 5.5 V 5
Output pin current IRESET 0.3 10 mA 5
Junction temperature (free-air temperature) TJ -40 125 °C 5
Voltage on VDD pin VDD -0.3 6 V 5
Voltage on RESET pin VRESET -0.3 6 V 5
Voltage on CT pin VCT -0.3 6 V 5
Voltage on SENSE pin VSENSE -0.3 6 V 5
Voltage on MR pin VMR -0.3 6 V 5
Current on RESET pin IRESET -40 40 mA 5
Operating junction temperature TJ -40 150 °C 5
Operating free-air temperature TA -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Junction-to-ambient thermal resistance RθJA 184.2 °C/W DSE (WSON) 6
Junction-to-case (top) thermal resistance RθJC(top) 30.6 °C/W DSE (WSON) 6
Junction-to-board thermal resistance RθJB 86.4 °C/W DSE (WSON) 6
Junction-to-top characterization parameter ΨJT 13.4 °C/W DSE (WSON) 6
Junction-to-board characterization parameter ΨJB 86.1 °C/W DSE (WSON) 6

CAD (KiCad official)

  • Symbol: TPS3703A4120DSERQ1
  • Footprint: Package_SON:WSON-6_1.5x1.5mm_P0.5mm
  • 3D model: WSON-6(1.5x1.5) (KiCad packages3D, STEP)
  • 3D model files: tps3703a4120dserq1-etched.step / tps3703a4120dserq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3703a4120dserq1.step / tps3703a4120dserq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (40 pp, sha256 05a6581745cb5982, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF