TPS3306-18D from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SENSE1	input	Sense voltage input 1; RESET is asserted while SENSE1 stays below its threshold VIT (2.93 V typ. for the TPS3306-18).
2	SENSE2	input	Sense voltage input 2; RESET is asserted while SENSE2 stays below its threshold VIT (1.68 V typ. for the TPS3306-18).
3	PFI	input	Power-fail comparator input, compared with an internal 1.25 V reference; the input must stay between 0 V and VDD + 0.3 V.
4	GND	power_in	Ground reference; all voltages are measured with respect to GND.
5	RESET	output	Active-low reset output with open-drain structure; it is asserted when VDD is above 1.1 V but SENSE1 or SENSE2 is below threshold, and it is held inactive by a 100 ms delay after both inputs rise above threshold.
6	PFO	output	Power-fail comparator output, open-drain; it goes low when PFI falls below 1.25 V and returns high above about 1.26 V.
7	WDI	input	Watchdog timer input; it must toggle within the 0.8 s typical time-out to prevent a reset, and leaving it unconnected disables the watchdog.
8	VDD	power_in	Supply voltage, specified from 2.7 V to 6 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-8
Category	Power Management (PMIC)
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VDD	2.7		6	V		6
Operating free-air temperature range	TA	-40		85	°C		6
Supply voltage	VDD			7	V	All voltage values with respect to GND	6
All other pins voltage		-0.3		7	V	All other pins, with respect to GND	6
PFI pin voltage		-0.3			V	PFI pin, maximum VDD + 0.3 V	6
Input voltage at WDI and PFI	VI	0			V	Maximum VDD + 0.3 V	6
Input voltage at SENSE1 and SENSE2	VI	0			V	Maximum (VDD + 0.3) VIT/1.25 V	6
Operating free-air temperature range	TA	-40		85	°C		6
Storage temperature range	Tstg	-65		150	°C		6
Soldering temperature				260	°C		6
Maximum low output current	IOL			5	mA		6
Maximum high output current	IOH			-5	mA		6
Input clamp current	IIK	-20		20	mA	VI < 0 or VI > VDD	6
Output clamp current	IOK	-20		20	mA	VO < 0 or VO > VDD	6
Low-level output voltage RESET, PFO	VOL			0.2	V	VDD = 2.7 V to 6 V, IOL = 20 µA	7
Low-level output voltage RESET, PFO	VOL			0.4	V	VDD = 3.3 V, IOL= 2 mA	7
Power-up reset voltage				0.4	V	VDD ≥ 1.1 V, IOL = 20 µA	7
Negative-going input threshold voltage SENSE1	VIT	2.86	2.93	3	V	VDD = 2.7 V to 6 V, TA = 0°C to +85°C	7
Negative-going input threshold voltage SENSE2	VIT	1.64	1.68	1.72	V	VDD = 2.7 V to 6 V, TA = 0°C to +85°C	7
Negative-going input threshold voltage SENSE1	VIT	2.86	2.93	3.02	V	VDD = 2.7 V to 6 V, TA = -40°C to +85°C	7
Negative-going input threshold voltage SENSE2	VIT	1.64	1.68	1.73	V	VDD = 2.7 V to 6 V, TA = -40°C to +85°C	7
Negative-going input threshold voltage PFI	VIT	1.22	1.25	1.28	V	TA = 0°C to +85°C	7
Negative-going input threshold voltage PFI	VIT	1.22	1.25	1.29	V	TA = -40°C to +85°C	7
Hysteresis PFI	Vhys		10		mV	VIT = 1.25 V	7
Hysteresis SENSEn	Vhys		15		mV	VIT = 1.68 V	7
Hysteresis SENSEn	Vhys		30		mV	VIT = 2.93 V	7
Average high-level input current WDI	IIH(AV)		100	150	µA	WDI = VDD = 6 V, Time average (dc = 88%)	7
Average low-level input current WDI	IIL(AV)		-15	-20	µA	WDI = 0 V, VDD = 6 V, Time average (dc = 12%)	7
High-level input current WDI	IIH		120	170	µA	WDI = VDD = 6 V	7
High-level input current SENSE1	IIH		5	8	µA	VSENSE1 = VDD = 6 V	7
High-level input current SENSE2	IIH		6	9	µA	VSENSE2 = VDD = 6 V	7
Low-level input current WDI	IIL		-120	-170	µA	WDI = 0 V, VDD = 6 V	7
Input current PFI	II	-25		25	nA	VDD = 6 V, 0 V ≤ VI ≤ VDD	7
Supply current	IDD		15	40	µA		7
Input capacitance	Ci		10		pF	VI = 0 V to VDD	7
Watchdog time-out	t(out)	0.5	0.8	1.2	s	VI(SENSEn) ≥ VIT + 0.2 V, See Timing Diagram	8
Delay time	td	70	100	140	ms	VI(SENSEn) ≥ VIT + 0.2 V, See Timing Diagram	8
Pulse width SENSEn	tw	6			µs	VSENSEnL = VIT, 0.2 V, VSENSEnH = VIT + 0.2 V	8
Pulse width WDI	tw	100			ns	VIH = 0.7 × VDD, VIL = 0.3 × VDD	8
Propagation delay time high-to-low SENSEn to RESET	tPHL		1	5	µs	VIH = VIT + 0.2 V, VIL = VIT, 0.2 V	8
Propagation delay time high-to-low PFI to PFO	tPHL		0.5	1	µs		8
Power rating, D package				725	mW	TA ≤ +25°C	6
Derating factor, D package			5.8		mW/°C	Above TA = +25°C	6
Power rating, D package				377	mW	TA = +85°C	6

CAD (KiCad official)

Symbol: TPS3306-18D
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: tps3306-18d-etched.step / tps3306-18d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3306-18d.step / tps3306-18d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (22 pp, sha256 e8d1ca90ec4d518e, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS3306-18D

Verified TPS3306-18D

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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