component
TPS3306-15DGK
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, VSSOP-8-0.65mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 29d ago |
| viewers | 29d ago |
| package.json | 29d ago |
| page.json | 29d ago |
| README.md | 29d ago |
| tps3306-15dgk-etched.glb | 29d ago |
| tps3306-15dgk-etched.step | 29d ago |
| tps3306-15dgk-hero.glb | 29d ago |
| tps3306-15dgk-hero.overlay.json | 29d ago |
| tps3306-15dgk.glb | 29d ago |
| tps3306-15dgk.kicad_mod | 29d ago |
| tps3306-15dgk.kicad_sym | 29d ago |
| tps3306-15dgk.lbr | 29d ago |
| tps3306-15dgk.step | 29d ago |
TPS3306-15DGK
Texas Instruments · Supervisor And Reset ICs · VSSOP-8-0.65mm
TPS3306-15DGK from Texas Instruments, in a VSSOP-8-0.65mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE1 | input | Sense voltage input 1 is monitored against its threshold VIT (typ. 2.93 V for TPS3306-15), RESET is held active while it stays below threshold, and its input range is 0 V to (VDD + 0.3 V) × VIT / 1.25 V. |
| 2 | SENSE2 | input | Sense voltage input 2 is monitored against its threshold VIT (typ. 1.4 V for TPS3306-15), RESET is held active while it stays below threshold, and its input range is 0 V to (VDD + 0.3 V) × VIT / 1.25 V. |
| 3 | PFI | input | Power-fail comparator input compared with an internal 1.25 V reference (typ.), with PFO going low below the threshold and about 10 mV hysteresis; the absolute input range is -0.3 V to VDD + 0.3 V, and PFI should be tied to ground if the comparator is unused. |
| 4 | GND | power_in | Ground reference for all pin voltages; all voltage values in the absolute maximum ratings are referenced to GND. |
| 5 | RESET | output | Active-low reset open-drain output that is defined from VDD ≥ 1.1 V, with a maximum low output current of 5 mA and a typical 100 ms delay after the sensed voltages return above threshold. |
| 6 | PFO | output | Power-fail comparator open-drain output that goes low when PFI falls below 1.25 V and has a maximum low output current of 5 mA. |
| 7 | WDI | input | Watchdog timer input where a low-to-high or high-to-low transition must occur within the 0.5 s to 1.2 s time-out (0.8 s typ.), VIH must be at least 0.7 × VDD and VIL at most 0.3 × VDD, and leaving it unconnected disables the watchdog. |
| 8 | VDD | power_in | Supply voltage with a recommended range of 2.7 V to 6 V and an absolute maximum of 7 V, and RESET is defined from VDD ≥ 1.1 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-8-0.65mm |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
TPS3306-15DGK - Footprint:
Package_SO:VSSOP-8_2.3x2mm_P0.5mm - 3D model: VSSOP-8-0.65mm (KiCad packages3D, STEP)
- 3D model files:
tps3306-15dgk-etched.step/tps3306-15dgk-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3306-15dgk.step/tps3306-15dgk.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (22 pp, sha256
163676c69bb32671, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).