component
TPS3110K33DBVR
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS3110K33DBVR
Texas Instruments · Supervisor And Reset ICs · SOT-23-6
TPS3110K33DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RESET | output | Active-low reset output with a push-pull output stage on the TPS3110 (the open-drain option applies to the TPS3103 and TPS3106). |
| 2 | GND | power_in | Ground reference; all voltage values in the datasheet are specified with respect to GND. |
| 3 | MR | input | Manual-reset input: pulling it low forces a reset, RESET stays low while MR is low and for the time-out period after MR goes high, and it may be left unconnected or tied to VDD when unused. |
| 4 | SENSE | input | A reset is asserted when the voltage at SENSE is lower than 0.551V, and SENSE should be connected to VDD if unused. |
| 5 | WDI | input | Watchdog timer input: if WDI remains high or low longer than the time-out period, a reset is triggered, and the timer clears on reset assertion or on any WDI edge. |
| 6 | VDD | power_in | Supply voltage input that powers the device and monitors its own voltage, with a recommended range of 0.9 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-6 |
| Category | Power Management (PMIC) |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 0.9 | 3.6 | V | 4 | ||
| SENSE voltage | VSENSE | 0 | V | max VDD | 4 | ||
| WDI, MR high-level input voltage | VIH | 0.7 | × VDD | 4 | |||
| WDI, MR low-level input voltage | VIL | 0.3 | × VDD | 4 | |||
| PFI voltage | PFI | 0 | 3.6 | V | 4 | ||
| Operating temperature | TJ | -40 | 125 | °C | 4 | ||
| Supply voltage | VDD | -0.3 | 4 | V | 4 | ||
| MR pin, RESET (push-pull) | VMR, VRESET | -0.3 | V | max VDD + 0.3 V | 4 | ||
| All other pins | -0.3 | 4 | V | with respect to GND | 4 | ||
| Maximum low output current | IOL | -5 | 5 | mA | 4 | ||
| Maximum high output current | IOH | -5 | 5 | mA | 4 | ||
| Input current | IIK | -10 | 10 | mA | VSENSE < 0V or VSENSE > VDD | 4 | |
| Output current | IOK | -10 | 10 | mA | VO < 0V or VO > VDD | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance | RθJA | 183.2 | °C/W | DBV (SOT-23) 6 pins | 5 | ||
| Negative-going input threshold voltage, TA = 25°C | VIT- | 2.919 | 2.941 | 2.963 | V | TPS31xxK33, TA = 25°C | 5 |
| Negative-going input threshold voltage, TA = -40°C to 125°C | VIT- | 2.823 | 3.058 | V | TPS31xxK33, TA = -40°C to 125°C | 5 | |
| Negative-going input threshold voltage SENSE, PFI, TA = 25°C | VIT-(S) | 0.542 | 0.551 | 0.559 | V | VDD ≥ 0.8V, TA = 25°C | 5 |
| Negative-going input threshold voltage SENSE, PFI, TA = -40°C to 125°C | VIT-(S) | 0.5 | 0.58 | V | VDD ≥ 0.8V, TA = -40°C to 125°C | 5 | |
| Hysteresis at VDD input | VHYS | 50 | mV | 2.5V ≤ VIT- < 3.3V | 5 | ||
| Hysteresis at SENSE, PFI input | VHYS(S) | 15 | mV | VDD ≥ 0.8V | 5 | ||
| High-level input current MR | IIH | -25 | 25 | nA | MR = VDD, VDD = 3.3V | 5 | |
| High-level input current SENSE, PFI, WDI | IIH | -25 | 25 | nA | SENSE, PFI, WDI = VDD, VDD = 3.3V | 5 | |
| Low-level input current MR | IIL | -47 | -33 | -25 | μA | MR = 0V, VDD = 3.3V | 6 |
| Low-level input current SENSE, PFI, WDI | IIL | -25 | 25 | nA | SENSE, PFI, WDI = 0V, VDD = 3.3V | 6 | |
| High-level output current at RESET (open-drain) | IOH | 200 | nA | VDD = VIT- + 0.2V, VOH = 3.3V | 6 | ||
| High-level output voltage | VOH | 0.8 | V | × VDD; VDD = 3.3V, IOH = -3mA | 5 | ||
| Low-level output voltage | VOL | 0.3 | V | VDD = 3.3V, IOL = 3mA | 5 | ||
| Low-level output voltage RESET only | VOL | 0.1 | V | VDD = 0.4V, IOL = 5μA | 5 | ||
| Supply current, TA = -40°C to 85°C, VDD > VIT-, VDD < 1.8V | IDD | 1.2 | 3 | μA | average current | 6 | |
| Supply current, TA = -40°C to 125°C, VDD > VIT-, VDD < 1.8V | IDD | 3 | μA | average current | 6 | ||
| Supply current, TA = -40°C to 85°C, VDD > VIT-, VDD > 1.8V | IDD | 2 | 4.5 | μA | average current | 6 | |
| Supply current, TA = -40°C to 125°C, VDD > VIT-, VDD > 1.8V | IDD | 5.5 | μA | average current | 6 | ||
| Supply current, TA = -40°C to 85°C, VDD < VIT-, VDD < 1.8V | IDD | 22 | μA | 6 | |||
| Supply current, TA = -40°C to 125°C, VDD < VIT-, VDD < 1.8V | IDD | 27 | μA | 6 | |||
| Supply current, TA = -40°C to 85°C, VDD < VIT-, VDD > 1.8V | IDD | 27 | μA | 6 | |||
| Supply current, TA = -40°C to 125°C, VDD < VIT-, VDD > 1.8V | IDD | 32 | μA | 6 | |||
| Internal pullup resistor at MR | RPU | 70 | 100 | 130 | kΩ | 6 | |
| Input capacitance at MR, SENSE, PFI, WDI | CIN | 1 | pF | VIN = 0V to VDD | 6 | ||
| Time-out period at WDI | tT(OUT) | 0.55 | 1.1 | 1.65 | s | VDD ≥ 0.85V | 7 |
| Pulse duration at VDD | tW | 20 | μs | VIH = 1.1 × VIT-, VIL = 0.9 × VIT-, VIT- = 0.86V | 7 | ||
| Pulse duration at MR | tW | 0.1 | μs | VDD ≥ VIT- + 0.2V, VIL = 0.3 × VDD, VIH = 0.7 × VDD | 7 | ||
| Pulse duration at SENSE | tW | 20 | μs | VDD ≥ VIT-, VIH = 1.1 × VIT-(S), VIL = 0.9 × VIT-(S) | 7 | ||
| Pulse duration at PFI | tW | 20 | μs | VDD ≥ 0.85V, VIH = 1.1 × VIT-(S), VIL = 0.9 × VIT-(S) | 7 | ||
| Pulse duration at WDI | tW | 0.3 | μs | VDD ≥ VIT-, VIL = 0.3 × VDD, VIH = 0.7 × VDD | 7 | ||
| Delay time | tD | 65 | 130 | 195 | ms | VDD ≥ 1.1 × VIT-, MR = 0.7 × VDD | 7 |
| Propagation delay high-to-low, VDD to RESET or RSTVDD | tPHL(VDD) | 40 | μs | VIH = 1.1 × VIT-, VIL = 0.9 × VIT- | 7 | ||
| Propagation delay high-to-low, SENSE to RESET or RSTSENSE | tPHL(SENSE) | 40 | μs | VDD ≥ 0.8V, VIH = 1.1 × VIT-, VIL = 0.9 × VIT- | 7 | ||
| Propagation delay high-to-low, PFI to PFO | tPHL(PFO) | 40 | μs | VDD ≥ 0.8V, VIH = 1.1 × VIT-, VIL = 0.9 × VIT- | 7 | ||
| Propagation delay low-to-high, PFI to PFO | tPLH(PFO) | 300 | μs | VDD ≥ 0.8V, VIH = 1.1 × VIT-, VIL = 0.9 × VIT- | 7 | ||
| Propagation delay high-to-low, MR to RESET, RSTVDD, RSTSENSE | tPHL(MR) | 1 | 5 | μs | VDD ≥ 1.1 × VIT-, VIL = 0.3 × VDD, VIH = 0.7 × VDD | 7 |
CAD (KiCad official)
- Symbol:
TPS3110K33DBVR - Footprint:
Package_TO_SOT_SMD:SOT-23-6 - 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files:
tps3110k33dbvr-etched.step/tps3110k33dbvr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps3110k33dbvr.step/tps3110k33dbvr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (33 pp, sha256
764f03d1f1ed5515, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).