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TPS3106E09DBVR

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Texas Instruments Monitors & Reset Circuits, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS3106E09DBVR

Texas Instruments · Monitors & Reset Circuits · SOT-23-6

TPS3106E09DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RSTVDD output Active-low open-drain reset output whose logic level depends only on the voltage at VDD and the status of MR.
2 GND power_in Ground.
3 MR input Manual-reset input; pull low to force a reset, RESET stays low while MR is low and for the time-out period after MR goes high, leave unconnected or connect to VDD when unused (absolute max -0.3 V to VDD + 0.3 V).
4 SENSE input A reset is asserted if the voltage at SENSE is lower than 0.551 V; connect to VDD if unused.
5 RSTSENSE output Active-low open-drain reset output whose logic level depends only on the voltage at SENSE and the status of MR.
6 VDD power_in Supply voltage that powers the device and monitors its own voltage, recommended 0.9 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-6
Category Power Supply Chip
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (abs max) VDD -0.3 4 V must not be operated at 3.6 V for more than 1000 h continuously 5
All other pins (abs max) -0.3 4 V 5
Maximum low output current IOL -5 5 mA 5
Maximum high output current IOH -5 5 mA 5
Input current IIK -10 10 mA VSENSE < 0 V or VSENSE > VDD 5
Output current IOK -10 10 mA VO < 0 V or VO > VDD 5
Operating junction temperature (abs max) TJ -40 125 °C 5
Storage temperature Tstg -65 150 °C 5
Supply voltage VDD 0.9 3.6 V For SENSE, PFI, WDI functions VDD ≥ 0.8 V 5
PFI voltage PFI 0 3.6 V 5
Input transition rise and fall rate at MR Δt/ΔV 100 ns/V at MR 5
Operating temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 183.2 °C/W DBV (SOT-23) 6 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 123.3 °C/W 6
Junction-to-board thermal resistance RθJB 29.4 °C/W 6
Negative-going input threshold voltage VIT- 0.854 0.86 0.866 V TPS31xxE09, TA = 25°C 6
Negative-going input threshold voltage VIT- 0.817 0.903 V TPS31xxE09, TA = -40°C to 125°C 6
Low-level output voltage VOL 0.3 V VDD = 0.9 V, IOL = 500 μA 6
Low-level output voltage RESET only VOL 0.1 V VDD = 0.4 V, IOL = 5 μA 6
Negative-going input threshold voltage SENSE VIT-(S) 0.542 0.551 0.559 V VDD ≥ 0.8 V, TA = 25°C 6
Negative-going input threshold voltage SENSE VIT-(S) 0.5 0.58 V VDD ≥ 0.8 V, TA = -40°C to 125°C 6
Hysteresis at VDD input VHYS 20 mV 0.8 V ≤ VIT- < 1.5 V 6
Temperature coefficient of VIT−, PFI, SENSE T(K) -0.019 -0.012 %/K TA = -40°C to 85°C 6
Hysteresis at SENSE, PFI input VHYS(S) 15 mV VDD ≥ 0.8 V 6
High-level input current MR IIH -25 25 nA MR = VDD, VDD = 3.3 V 6
High-level input current SENSE IIH -25 25 nA SENSE = VDD, VDD = 3.3 V 6
Low-level input current MR IIL -47 -33 -25 μA MR = 0 V, VDD = 3.3 V 7
Low-level input current SENSE IIL -25 25 nA SENSE = 0 V, VDD = 3.3 V 7
High-level output current at RESET IOH 200 nA Open-drain VDD = VIT- + 0.2 V, VOH = 3.3 V 7
Supply current IDD 1.2 3 μA TA = -40°C to 85°C, VDD > VIT- (average current), VDD < 1.8 V 7
Supply current IDD 3 μA TA = -40°C to 125°C, VDD > VIT- (average current), VDD < 1.8 V 7
Supply current IDD 22 μA TA = -40°C to 85°C, VDD < VIT-, VDD < 1.8 V 7
Supply current IDD 27 μA TA = -40°C to 125°C, VDD < VIT-, VDD < 1.8 V 7
Internal pullup resistor at MR 70 100 130 kΩ 7
Input capacitance at MR, SENSE, PFI, WDI CIN 1 pF VIN = 0 V to VDD 7
Pulse duration at VDD tW 20 μs VIH = 1.1 × VIT-, VIL = 0.9 × VIT-, VIT- = 0.86 V 8
Pulse duration at MR tW 0.1 μs VDD ≥ VIT- + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD 8
Pulse duration at SENSE tW 20 μs VDD ≥ VIT-, VIH = 1.1 × VIT − (S), VIL = 0.9 × VIT − (S) 8
Delay time tD 65 130 195 ms VDD ≥ 1.1 × VIT-, MR = 0.7 × VDD 8
Propagation delay VDD to RSTVDD tPHL(VDD) 40 μs VIH = 1.1 × VIT-, VIL = 0.9 × VIT- 8
Propagation delay SENSE to RSTSENSE tPHL(SENSE) 40 μs VDD ≥ 0.8 V, VIH = 1.1 × VIT-, VIL = 0.9 × VIT- 8
Propagation delay MR to RSTVDD, RSTSENSE tPHL(MR) 1 5 μs VDD ≥ 1.1 × VIT-, VIL = 0.3 × VDD, VIH = 0.7 × VDD 8

CAD (KiCad official)

  • Symbol: TPS3106E09DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: tps3106e09dbvr-etched.step / tps3106e09dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3106e09dbvr.step / tps3106e09dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 2859afb3fa14b04d, retrieved 2026-10-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF