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TPS3103K33DBVR

Public Made by Adom

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Texas Instruments Monitors & Reset Circuits, SOT-23-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS3103K33DBVR

Texas Instruments · Monitors & Reset Circuits · SOT-23-6

TPS3103K33DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RESET output Active-low reset output with either push-pull or open-drain output stage; the TPS3103 has an open-drain RESET output.
2 GND power_in Ground reference pin for the device.
3 MR input Manual-reset input: pull low to force a reset, and RESET remains low while MR is low and for the time-out period after MR goes high; leave unconnected or connect to VDD when unused.
4 PFI input Power-fail input compares to 0.551V with no additional delay; connect to VDD if not used.
5 PFO output Power-fail output that goes high when the voltage at PFI rises above 0.551V.
6 VDD power_in Supply voltage that powers the device and monitors its own voltage; recommended operating range is 0.9V to 3.6V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-6
Category Power Management ICs
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Negative-going input threshold voltage TPS31xxK33 (TA = 25°C) VIT- 2.919 2.941 2.963 V TA = 25°C 5
Negative-going input threshold voltage TPS31xxK33 (TA = -40°C to 125°C) VIT- 2.823 3.058 V TA = -40°C to 125°C 5
Negative-going input threshold voltage SENSE, PFI (TA = 25°C) VIT-(S) 0.542 0.551 0.559 V VDD ≥ 0.8V, TA = 25°C 5
Negative-going input threshold voltage SENSE, PFI (TA = -40°C to 125°C) VIT-(S) 0.5 0.58 V VDD ≥ 0.8V, TA = -40°C to 125°C 5
High-level input current MR IIH -25 25 nA MR = VDD, VDD = 3.3V 5
High-level input current SENSE, PFI, WDI IIH -25 25 nA SENSE, PFI, WDI = VDD, VDD = 3.3V 5
Low-level input current MR IIL -47 -33 -25 μA MR = 0V, VDD = 3.3V 6
Low-level input current SENSE, PFI, WDI IIL -25 25 nA SENSE, PFI, WDI = 0V, VDD = 3.3V 6
Supply current (TA = -40°C to 85°C, VDD > VIT-, VDD < 1.8V) IDD 1.2 3 μA TA = -40°C to 85°C, VDD > VIT- (average current), VDD < 1.8V 6
Supply current (TA = -40°C to 125°C, VDD > VIT-, VDD < 1.8V) IDD 3 μA TA = -40°C to 125°C, VDD > VIT- (average current), VDD < 1.8V 6
Supply current (TA = -40°C to 85°C, VDD > VIT-, VDD > 1.8V) IDD 2 4.5 μA TA = -40°C to 85°C, VDD > VIT- (average current), VDD > 1.8V 6
Supply current (TA = -40°C to 125°C, VDD > VIT-, VDD > 1.8V) IDD 5.5 μA TA = -40°C to 125°C, VDD > VIT- (average current), VDD > 1.8V 6
Supply current (TA = -40°C to 85°C, VDD < VIT-, VDD < 1.8V) IDD 22 μA TA = -40°C to 85°C, VDD < VIT-, VDD < 1.8V 6
Supply current (TA = -40°C to 125°C, VDD < VIT-, VDD < 1.8V) IDD 27 μA TA = -40°C to 125°C, VDD < VIT-, VDD < 1.8V 6
Supply current (TA = -40°C to 85°C, VDD < VIT-, VDD > 1.8V) IDD 27 μA TA = -40°C to 85°C, VDD < VIT-, VDD > 1.8V 6
Supply current (TA = -40°C to 125°C, VDD < VIT-, VDD > 1.8V) IDD 32 μA TA = -40°C to 125°C, VDD < VIT-, VDD > 1.8V 6
Internal pullup resistor at MR 70 100 130 kΩ 6
Time-out period at WDI tT(OUT) 0.55 1.1 1.65 s At RL = 1MΩ, CL = 50pF, TA = -40°C to 85°C; VDD ≥ 0.85V 7
Delay time tD 65 130 195 ms VDD ≥ 1.1 × VIT-, MR = 0.7 × VDD 7
Supply voltage VDD 0.9 3.6 V 4
Operating temperature TJ -40 125 °C Over operating junction temperature range 4
Supply voltage VDD -0.3 4 V All voltage values with respect to GND 4
MR pin, RESET (push-pull) VMR, VRESET -0.3 V Upper limit printed as VDD + 0.3 V 4
All other pins -0.3 4 V All voltage values with respect to GND 4
Maximum low output current IOL -5 5 mA 4
Maximum high output current IOH -5 5 mA 4
Input current IIK -10 10 mA VSENSE < 0V or VSENSE > VDD 4
Output current IOK -10 10 mA VO < 0V or VO > VDD 4
Temperature operating junction TJ -40 125 °C Operating junction temperature range 4
Temperature storage Tstg -65 150 °C 4
Junction-to-ambient thermal resistance RθJA 183.2 °C/W DBV (SOT-23), 6 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 123.3 °C/W DBV (SOT-23), 6 pins 5
Junction-to-board thermal resistance RθJB 29.4 °C/W DBV (SOT-23), 6 pins 5
Junction-to-top characterization parameter ψJT 20.5 °C/W DBV (SOT-23), 6 pins 5
Junction-to-board characterization parameter ψJB 29 °C/W DBV (SOT-23), 6 pins 5

CAD (KiCad official)

  • Symbol: TPS3103K33DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: tps3103k33dbvr-etched.step / tps3103k33dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps3103k33dbvr.step / tps3103k33dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (33 pp, sha256 764f03d1f1ed5515, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF