component
TPS2HB16FQPWPRQ1
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
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TPS2HB16FQPWPRQ1
Texas Instruments · Power Distribution Switches · HTSSOP-16-EP
TPS2HB16FQPWPRQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground; reverse ground current IGND is limited to -50 mA when VBB < 0 V. |
| 2 | SNS | output | Analog sense output that reports load current on version F, and goes to the predefined ISNSFH level on a fault; sense pin voltage is limited to -1 V to 18 V absolute maximum. |
| 3 | LATCH | input | Sets fault handling behavior (latched or auto-retry); LATCH voltage is limited to -1 V to 5.5 V recommended. |
| 4 | EN1 | input | Channel 1 control input, active high; enable voltage is limited to -1 V to 5.5 V recommended. |
| 5 | FLT1 | output | Open-drain fault indication for channel 1, triggered by channel 1 overcurrent, overtemperature or open load. |
| 6 | VOUT1 | power_out | Channel 1 output to the load. |
| 7 | VOUT1 | power_out | Channel 1 output to the load. |
| 8 | VOUT1 | power_out | Channel 1 output to the load. |
| 9 | VOUT2 | power_out | Channel 2 output to the load. |
| 10 | VOUT2 | power_out | Channel 2 output to the load. |
| 11 | VOUT2 | power_out | Channel 2 output to the load. |
| 12 | FLT2 | output | Open-drain fault indication for channel 2, triggered by channel 2 overcurrent, overtemperature or open load. |
| 13 | EN2 | input | Channel 2 control input, active high; enable voltage is limited to -1 V to 5.5 V recommended. |
| 14 | SEL1 | input | Diagnostics select 1; no functionality on version F, so tie to device ground through a 10 kΩ resistor. |
| 15 | SEL2 | input | Diagnostics select 2; selects the channel reported on the SNS output, with select voltage limited to -1 V to 5.5 V recommended. |
| 16 | DIA_EN | input | Diagnostic enable, active high; diagnostic enable voltage is limited to -1 V to 5.5 V recommended. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16-EP |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum continuous supply voltage | VBB | 36 | V | 6 | |||
| Load dump voltage | VLD | 40 | V | ISO16750-2:2010(E) | 6 | ||
| Reverse battery voltage | VRev | -18 | V | t ≤ 3 minutes | 6 | ||
| Enable pin voltage | VEN1, VEN2 | -1 | 7 | V | 6 | ||
| Sense pin voltage | VSNS | -1 | 18 | V | 6 | ||
| Reverse ground current | IGND | -50 | mA | VBB < 0 V | 6 | ||
| Energy dissipation during turnoff, single pulse | ETOFF | 50 | mJ | Single pulse, one channel, LOUT = 5 mH, TJ,start = 125°C | 6 | ||
| Maximum junction temperature | TJ | 150 | °C | 6 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Nominal supply voltage | VBB | 6 | 18 | V | 6 | ||
| Extended supply voltage | VBB | 3 | 28 | V | 6 | ||
| Enable voltage | VEN1, VEN2 | -1 | 5.5 | V | 6 | ||
| Operating free-air temperature | TA | -40 | 125 | °C | 6 | ||
| VBB clamp voltage | VBBCLAMP | 58 | 76 | V | 7 | ||
| VDS clamp voltage | VDSCLAMP | 40 | 46 | V | 7 | ||
| VBB undervoltage lockout falling | VUVLOF | 2 | 3 | V | Measured with respect to the GND pin of the device | 7 | |
| VBB undervoltage lockout rising | VUVLOR | 2.2 | 3 | V | Measured with respect to the GND pin of the device | 7 | |
| Standby current | ISB | 0.5 | µA | VBB = 13.5 V, TJ = 25°C, VENx = VDIA_EN = 0 V, VOUT = 0 V | 7 | ||
| Standby current | ISB | 4 | µA | VBB = 13.5 V, TJ = 125°C, VENx = VDIA_EN = 0 V, VOUT = 0 V | 7 | ||
| Continuous load current, per channel | ILNOM | 5 | A | Two channels enabled, TAMB = 70°C | 7 | ||
| Continuous load current, per channel | ILNOM | 7 | A | One channel enabled, TAMB = 70°C | 7 | ||
| Output leakage current per channel | IOUT(standby) | 0.01 | 0.5 | µA | VBB = 13.5 V, TJ = 25°C, VENx = VDIA_EN = 0 V, VOUT = 0 V | 7 | |
| Output leakage current per channel | IOUT(standby) | 1.5 | µA | VBB = 13.5 V, TJ = 125°C, VENx = VDIA_EN = 0 V, VOUT = 0 V | 7 | ||
| Current consumption in diagnostic mode | IDIA | 3 | 6 | mA | VBB = 13.5 V, ISNS = 0 mA, VENx = 0 V, VDIA_EN = 5 V, VOUT = 0V | 7 | |
| Quiescent current | IQ | 3 | 6 | mA | VBB = 13.5 V, VENx = VDIA_EN = 5 V, IOUTx = 0 A | 7 | |
| Standby mode delay time | tSTBY | 12 | 17 | 22 | ms | VENx = VDIA_EN = 0 V to standby | 7 |
| On-resistance | RON | 16 | mΩ | TJ = 25°C, 6 V ≤ VBB ≤ 28 V, IOUT1 = IOUT2 > 1 A | 7 | ||
| On-resistance | RON | 40 | mΩ | TJ = 150°C, 6 V ≤ VBB ≤ 28 V, IOUT1 = IOUT2 > 1 A | 7 | ||
| On-resistance | RON | 30 | mΩ | TJ = 25°C, 3 V ≤ VBB ≤ 6 V, IOUT1 = IOUT2 > 1 A | 7 | ||
| On-resistance during reverse polarity | RON(REV) | 16 | mΩ | TJ = 25°C, -18 V ≤ VBB ≤ -8 V | 7 | ||
| On-resistance during reverse polarity | RON(REV) | 40 | mΩ | TJ = 105°C, -18 V ≤ VBB ≤ -8 V | 7 | ||
| Current sense ratio IOUTx/ISNS | KSNS | 3000 | IOUTX = 1 A | 7 | |||
| Current sense accuracy | ISNSI | -5 | 5.3 | % | VEN = VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X, IOUT = 6 A | 8 | |
| Current sense accuracy | ISNSI | -6 | 6.3 | % | VEN = VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X, IOUT = 300 mA | 8 | |
| Current sense accuracy | ISNSI | -9 | 9.6 | % | VEN = VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X, IOUT = 100 mA | 8 | |
| Current sense accuracy | ISNSI | -19.5 | 18.7 | % | VEN = VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X, IOUT = 50 mA | 8 | |
| Current sense accuracy | ISNSI | -59.3 | 53.1 | % | VEN = VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X, IOUT = 20 mA | 8 | |
| ISNS fault high-level | ISNSFH | 4 | 4.5 | 5.3 | mA | VDIA_EN = 5 V, VSEL1 = 0 V, VSEL2 = X | 8 |
| Current limit threshold, Version F, TJ = -40°C to 60°C | ICL | 51.65 | 60 | 76.32 | A | Device Version F, TJ = -40°C to 60°C | 8 |
| Current limit threshold, Version F, TJ = 150°C | ICL | 42.16 | 48 | 57.6 | A | Device Version F, TJ = 150°C | 8 |
| Open-load detection voltage | VOL | 2 | 3 | 4 | V | VENx = 0 V, VDIA_EN = 5 V | 8 |
| OL and STB indication time from ENx falling | tOL1 | 300 | 500 | 700 | µs | VENx = 5 V to 0 V, VDIA_EN = 5 V, VSEL1 = 0 V, IOUT = 0 mA, VOUTx = 4 V | 8 |
| OL and STB indication time from DIA_EN rising | tOL2 | 50 | µs | VENx = 0 V, VDIA_EN = 0 V to 5 V, VSEL1 = 0 V, IOUT = 0 mA, VOUTx = 4 V | 8 | ||
| OL and STB indication time from VOUT rising | tOL3 | 50 | µs | VENx = 0 V, VDIA_EN = 5 V, VSEL1 = 0 V, IOUT = 0 mA, VOUTx = 0 V to 4 V | 8 | ||
| Thermal shutdown | TABS | 150 | °C | VBB = 3 V to 28 V | 9 | ||
| Relative thermal shutdown | TREL | 50 | °C | 9 | |||
| Thermal shutdown hysteresis | THYS | 28 | °C | 9 | |||
| Fault shutdown indication-time | tFAULT | 50 | µs | VDIA_EN = 5 V, time between switch shutdown and ISNS settling at ISNSFH | 9 | ||
| Retry time | tRETRY | 1 | 2 | 3 | ms | Time from fault shutdown until switch re-enable (thermal shutdown or current limit) | 9 |
| Turnon time | tON | 39 | 87 | 145 | µs | VBB = 13.5 V, RL ≤ 4 Ω, 50% EN rising to 80% VOUT rising | 10 |
| Turnoff time | tOFF | 39 | 87 | 147 | µs | VBB = 13.5 V, RL ≤ 4 Ω, 50% EN rising to 80% VOUT rising | 10 |
| VOUTx rising slew rate | SRR | 0.1 | 0.4 | 0.7 | V/µs | VBB = 13.5 V, 20% to 80% of VOUT, RL ≤ 4 Ω | 10 |
| VOUTx falling slew rate | SRF | 0.1 | 0.4 | 0.7 | V/µs | VBB = 13.5 V, 80% to 20% of VOUT, RL ≤ 4 Ω | 10 |
| Input voltage low-level, ENx | VIL, ENx | 0.8 | V | No GND network diode | 9 | ||
| Input voltage high-level, ENx | VIH, ENx | 2 | V | No GND network diode | 9 | ||
| Junction-to-ambient thermal resistance | RθJA | 32.9 | °C/W | PWP (HTSSOP) 16 pins, 4-layer PCB per JESD51-5 and JESD51-7 | 7 | ||
| Junction-to-board thermal resistance | RθJB | 9 | °C/W | PWP (HTSSOP) 16 pins, 4-layer PCB per JESD51-5 and JESD51-7 | 7 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2 | °C/W | PWP (HTSSOP) 16 pins, 4-layer PCB per JESD51-5 and JESD51-7 | 7 |
CAD (KiCad official)
- Symbol:
TPS2HB16FQPWPRQ1 - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
tps2hb16fqpwprq1-etched.step/tps2hb16fqpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2hb16fqpwprq1.step/tps2hb16fqpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (58 pp, sha256
83860ae4e964362c, retrieved 2026-11-06, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).