component
TPS27SA08CPWPR
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, HTSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 21d ago |
| viewers | 21d ago |
| package.json | 21d ago |
| page.json | 21d ago |
| README.md | 21d ago |
| tps27sa08cpwpr-etched.glb | 21d ago |
| tps27sa08cpwpr-etched.step | 21d ago |
| tps27sa08cpwpr-hero.glb | 21d ago |
| tps27sa08cpwpr-hero.overlay.json | 21d ago |
| tps27sa08cpwpr.glb | 21d ago |
| tps27sa08cpwpr.kicad_mod | 21d ago |
| tps27sa08cpwpr.kicad_sym | 21d ago |
| tps27sa08cpwpr.lbr | 21d ago |
| tps27sa08cpwpr.step | 21d ago |
TPS27SA08CPWPR
Texas Instruments · Power Distribution Switches · HTSSOP-16
TPS27SA08CPWPR from Texas Instruments, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground pin; with a ground protection network (DGND/RGND) the device ground is offset from the microcontroller ground. |
| 2 | SNS | output | Analog sense output that carries a current proportional to load current, supply voltage, or device temperature (selected by SEL1/SEL2) or the fault level ISNSFH; it has an internal clamp at VSNSclamp (5.9 V typ) and must be terminated to GND through 1 kΩ if unused. |
| 3 | LATCH | input | Sets the fault-handling behavior to latched or automatic retry, with VIL max 0.8 V and VIH min 2 V; leave floating or tie to GND through RPROT for auto-retry. |
| 4 | EN | input | Active-high switch control input with VIL max 0.8 V, VIH min 2 V, and an internal 1 MΩ pull-down; the recommended input voltage range is -1 V to 5.5 V. |
| 5 | ST | output | Open-drain, active-low switch diagnostic feedback that is high-impedance without fault and pulled low on fault, with VOL max 0.4 V at 1 mA. |
| 6 | VOUT | output | Switch output; all six VOUT pins (6 to 11) must be shorted together on the PCB and routed symmetrically to the power FET. |
| 7 | VOUT | output | Switch output; all six VOUT pins (6 to 11) must be shorted together on the PCB and routed symmetrically to the power FET. |
| 8 | VOUT | output | Switch output; all six VOUT pins (6 to 11) must be shorted together on the PCB and routed symmetrically to the power FET. |
| 9 | VOUT | output | Switch output; all six VOUT pins (6 to 11) must be shorted together on the PCB and routed symmetrically to the power FET. |
| 10 | VOUT | output | Switch output; all six VOUT pins (6 to 11) must be shorted together on the PCB and routed symmetrically to the power FET. |
| 11 | VOUT | output | Switch output; all six VOUT pins (6 to 11) must be shorted together on the PCB and routed symmetrically to the power FET. |
| 12 | NC | unconnected | No internal connection. |
| 13 | NC | unconnected | No internal connection. |
| 14 | SEL1 | input | Diagnostic select 1 that chooses between VBB and TJ sensing; if unused, leave floating or tie to GND through RPROT, which leaves only load diagnostics available. |
| 15 | SEL2 | input | Diagnostic select 2; when held at 0 V the VBB measurement diagnostic is unavailable, and if unused it should be tied to GND through RPROT. |
| 16 | DIA_EN | input | Active-high diagnostic enable; when unused, analog sensing, open-load and short-to-supply diagnostics are unavailable, and it should be left floating or tied to GND through RPROT. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16 |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Max continuous supply voltage | VBB | 36 | V | 6 | |||
| Max supply voltage, long transient | VTR1 | 40 | V | duration < 300ms | 6 | ||
| Max transient voltage at supply input, VBB to IC GND | VTR2 | 54 | V | 6 | |||
| Reverse supply voltage | VRev | -36 | V | VREV ≤ 3 min, GND network | 6 | ||
| Enable pin voltage | VEN | -1 | 7 | V | 6 | ||
| LATCH pin voltage | VLATCH | -1 | 7 | V | 6 | ||
| Status pin voltage | VST | -1 | 7 | V | 6 | ||
| Diagnostic enable pin voltage | VDIA_EN | -1 | 7 | V | 6 | ||
| Sense pin voltage | VSNS | -1 | 7 | V | 6 | ||
| Select pin voltage | VSEL1, VSEL2 | -1 | 7 | V | 6 | ||
| Reverse current flowing into GND | IGND | -50 | mA | VBB < 0V | 6 | ||
| Max junction temperature | TJ | 150 | °C | 6 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Nominal supply voltage (recommended) | VBB | 8 | 36 | V | 6 | ||
| Enable voltage (recommended) | VEN | -1 | 5.5 | V | 6 | ||
| LATCH voltage (recommended) | VLATCH | -1 | 5.5 | V | 6 | ||
| Diagnostic enable voltage (recommended) | VDIA_EN | -1 | 5.5 | V | 6 | ||
| Select voltage (recommended) | VSEL1, VSEL2 | -1 | 5.5 | V | 6 | ||
| Status voltage (recommended) | VST | 0 | 5.5 | V | 7 | ||
| Sense voltage (recommended) | VSNS | -1 | V | 7 | |||
| Continuous load current | IMAX | 0 | 10 | A | TA = 70°C | 7 | |
| VDS clamp voltage | VClamp | 40 | 58 | V | 7 | ||
| VBB undervoltage lockout falling | VUVLOF | 2.5 | 3 | V | 7 | ||
| VBB undervoltage lockout rising | VUVLOR | 2.5 | 3 | V | 7 | ||
| Output leakage current, 25°C | IOUT_OFF | 0.01 | 0.5 | µA | VBB = 24V, TJ = 25°C, VEN = VDIA_EN = 0V, VOUT = 0V | 7 | |
| Current in diagnostic mode | IDIA | 3 | 6 | mA | VBB = 24V, ISNS = 0mA, VEN = 0V, VDIA_EN = 5V, VOUT = 0V | 7 | |
| Quiescent current | IQ | 2.4 | 5.2 | mA | VBB = 24V, VEN = 5V, VDIA_EN = 0V, IOUT = 0A, VSELX = 0V | 7 | |
| Current sense accuracy at 8A | ISNSI | -5 | 5 | % | VEN = VDIA_EN = 5V, VSEL1 = VSEL2 = 0V, IOUT = 8A | 8 | |
| Current sense accuracy at 3A | ISNSI | -5 | 5 | % | VEN = VDIA_EN = 5V, VSEL1 = VSEL2 = 0V, IOUT = 3A | 8 | |
| Current sense accuracy at 780mA | ISNSI | -5 | 5 | % | VEN = VDIA_EN = 5V, VSEL1 = VSEL2 = 0V, IOUT = 780mA | 8 | |
| Current sense accuracy at 300mA | ISNSI | -12 | 12 | % | VEN = VDIA_EN = 5V, VSEL1 = VSEL2 = 0V, IOUT = 300mA | 8 | |
| Current sense accuracy at 100mA | ISNSI | -42 | 42 | % | VEN = VDIA_EN = 5V, VSEL1 = VSEL2 = 0V, IOUT = 100mA | 8 | |
| ISNS fault high level | ISNSFH | 6 | 6.9 | 7.6 | mA | VDIA_EN = 5V, VSEL1 = 0V, VSEL2 = 0 | 8 |
| ISNS leakage current | ISNSleak | 0 | 1 | µA | VDIA_EN = 0V | 8 | |
| Current limit threshold, current-limit loop on | ICL | 17 | 22.2 | 27.8 | A | TJ = -40°C | 8 |
| Current limit threshold, current-limit loop on | ICL | 15 | 20 | 25 | A | TJ = 25°C | 8 |
| Current limit threshold, current-limit loop on | ICL | 12.8 | 16 | 20 | A | TJ = 125°C | 9 |
| Open-load detection voltage | VOL | 2 | 2.5 | 4 | V | VEN = 0V, VDIA_EN = 5V | 9 |
| OL and STB indication time, switch disabled, from EN falling edge | tOL1 | 300 | 500 | 700 | µs | VEN = 5V to 0V, VDIA_EN = 5V, VSELx = 00, IOUT = 0mA, VOUT = 4V | 9 |
| Retry time, fault shutdown to switch re-enable | tRETRY | 1 | 2 | 3 | ms | thermal shutdown, current limit and energy limit | 9 |
| EN input voltage low level | VIL, EN | 0.8 | V | 9 | |||
| EN input voltage high level | VIH, EN | 2 | V | 无 GND 网络二极管 | 9 | ||
| DIA_EN input voltage low level | VIL, DIA_EN | 0.8 | V | 无 GND 网络二极管 | 9 | ||
| DIA_EN input voltage high level | VIH, DIA_EN | 2 | V | 无 GND 网络二极管 | 9 | ||
| SELx input voltage low level | VIL, SELx | 0.8 | V | 无 GND 网络二极管 | 9 | ||
| SELx input voltage high level | VIH, SELx | 2 | V | 9 | |||
| LATCH input voltage low level | VIL, LATCH | 0.8 | V | 无 GND 网络二极管 | 9 | ||
| LATCH input voltage high level | VIH, LATCH | 2 | V | 无 GND 网络二极管 | 9 | ||
| ST output voltage low level | VOL, ST | 0.4 | V | IST = 1mA | 10 | ||
| Turn-on delay time | tDR | 20 | 70 | 100 | µs | VBB = 24V, RL = 8Ω | 10 |
| Turn-off delay time | tDF | 20 | 50 | 125 | µs | VBB = 24V, RL = 8Ω | 10 |
| VOUT rising slew rate | SRR | 0.1 | 0.35 | 0.8 | V/µs | VBB = 24V, VOUT 20% to 80%, RL = 8Ω | 10 |
| VOUT falling slew rate | SRF | 0.2 | 0.5 | 0.9 | V/µs | VBB = 24V, VOUT 80% to 20%, RL = 8Ω | 10 |
| Turn-on time | tON | 39 | 100 | 180 | µs | VBB = 24V, RL = 8Ω | 10 |
| Turn-off time | tOFF | 39 | 90 | 180 | µs | VBB = 24V, RL = 8Ω | 10 |
| Turn-on and turn-off matching | tON - tOFF | -80 | 0 | 80 | µs | 200µs enable pulse | 10 |
| Junction-to-ambient thermal resistance | RθJA | 32.8 | °C/W | JESD51-5/JESD51-7, 4-layer PCB | 7 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 30.7 | °C/W | JESD51-5/JESD51-7, 4-layer PCB | 7 | ||
| Junction-to-board thermal resistance | RθJB | 9.3 | °C/W | JESD51-5/JESD51-7, 4-layer PCB | 7 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 1 | °C/W | JESD51-5/JESD51-7, 4-layer PCB | 7 |
CAD (KiCad official)
- Symbol:
TPS27SA08CPWPR - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
tps27sa08cpwpr-etched.step/tps27sa08cpwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps27sa08cpwpr.step/tps27sa08cpwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (51 pp, sha256
a180e810c723eaed, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).