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TPS274C65ASHRHAR

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Texas Instruments Power Distribution Switches, VQFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS274C65ASHRHAR

Texas Instruments · Power Distribution Switches · VQFN-40(6x6)

TPS274C65ASHRHAR from Texas Instruments, in a VQFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 READY output Logic-low output indicating the IC is ready for SPI data transmission; connect to the IC GND pin through a resistor.
2 FLT output Open-drain fault output that signals a fault on any one or more channels and must be pulled up to the VDD pin.
3 DO_EN input Setting this pin low disables all outputs; set high to enable SPI-based output control (internal pull-down).
4 VDD power_in Logic supply input; recommended operating range is 3.0 V to 5.5 V, and an external regulator on VDD must derive its supply from the same VS supply.
5 GND power_in Device ground.
6 ISNS output SNS current output that requires a parallel RC network to the IC GND pin.
7 SDO output SPI data output from the device; it is three-stated when CS is high.
8 SDI input SPI data input for the secondary (device) side.
9 SCLK input SPI clock input; maximum SPI clock rate is 10 MHz.
10 CS input SPI chip select input.
11 RCB3 output Gate connection for the reverse current blocking FET of channel 3.
12 OUT3 output Output voltage for channel 3.
13 OUT3 output Output voltage for channel 3.
14 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
15 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
16 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
17 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
18 OUT4 output Output voltage for channel 4.
19 OUT4 output Output voltage for channel 4.
20 RCB4 output Gate connection for the reverse current blocking FET of channel 4.
21 GND power_in Device ground.
22 LEDOUT1 output LED matrix select driver output for channel 1.
23 LEDOUT2 output LED matrix select driver output for channel 2.
24 LEDOUT3 output LED matrix select driver output for channel 3.
25 LEDOUT4 output LED matrix select driver output for channel 4.
26 DNC unconnected Do not connect.
27 DNC unconnected Do not connect.
28 DSPI input Pulling this pin high configures the device in daisy-chain SPI mode.
29 REG_EN input Internal regulator enable: float to enable; tie to GND to disable and supply VDD externally.
30 ADDCFG input SPI address configuration pin that sets the 3-bit device address (up to 8 devices) via a resistor to GND (<1% tolerance recommended); leave floating in daisy-chain mode.
31 RCB2 output Gate connection for the reverse current blocking FET of channel 2.
32 OUT2 output Output voltage for channel 2.
33 OUT2 output Output voltage for channel 2.
34 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
35 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
36 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
37 VS power_in 24 V switch supply input to the IC; absolute maximum continuous supply is 40 V.
38 OUT1 output Output voltage for channel 1.
39 OUT1 output Output voltage for channel 1.
40 RCB1 output Gate connection for the reverse current blocking FET of channel 1.
41 GND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40(6x6)
Category Power Management (PMIC)
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
CHx ICL current limitation level, H version (Setting = 2.45 A) ICLx 2.06 2.45 2.84 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 2.26 A) ICLx 2.01 2.26 2.88 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 2.07 A) ICLx 1.74 2.07 2.4 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 1.9 A) ICLx 1.6 1.9 2.3 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 1.71 A) ICLx 1.42 1.71 1.94 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 1.52 A) ICLx 1.2 1.52 1.78 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 1.33 A) ICLx 1.06 1.33 1.6 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 1.15 A) ICLx 0.94 1.15 1.36 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.96 A) ICLx 0.78 0.96 1.1 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.86 A) ICLx 0.72 0.86 1.02 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.76 A) ICLx 0.64 0.76 0.88 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.67 A) ICLx 0.53 0.67 0.78 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.57 A) ICLx 0.47 0.57 0.65 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.48 A) ICLx 0.4 0.48 0.55 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.38 A) ICLx 0.3 0.38 0.45 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx ICL current limitation level, H version (Setting = 0.29 A) ICLx 0.22 0.29 0.39 A Regulated current at short circuit RL < 200 mohms when enabled, VDD = 3.3 V 11
CHx VDS clamp voltage VDS_Clamp 40 44 50 V FET current = 10 mA, VS = 24 V 8
CHx VDS clamp voltage VDS_Clamp 33 37 41 V FET current = 10 mA, VS = 10 V 8
VS undervoltage protection falling VS_UVPF 8.6 9 9.3 V Measured with respect to GND pin of the device, all channels ON; output FETs turned off at VS less than this threshold 8
VS undervoltage protection recovery rising VS_UVPR 9.5 10 10.3 V Measured with respect to GND pin of the device, all channels ON; output FETs turned ON at VS more than this threshold 8
VDD output voltage (internal regulator enabled) VVDD 3.1 3.3 3.6 V 6 V ≤ VS ≤ 36 V, IVDD < 20 mA; includes load and line regulation across the range 10
Current limit of internal regulator ICL_VDD 25 50 mA 6 V ≤ VS ≤ 36 V 10
VDD quiescent current, SCLK ON, all diagnostics disabled, external VDD VDD IQ 1.3 1.6 mA VS ≤ 36 V, VDD = 5.5 V; all channels enabled, IOUTx = 0 A 9
CHx current sense current (diagnostic enabled, RSNS = 1 kΩ) ISNSI CHx 1.69 1.73 1.77 mA Current sense diagnostic enabled, RSNS = 1 kΩ; IOUTx = 2 A 10
Output leakage current (per channel) IOUT(OFF) 0 0.8 10 µA VS ≤ 36 V, VOUT = 0; channel disabled, diagnostics disabled, Tj ≤ 125°C 9
TSD thermal shutdown TABS 160 185 210 °C 12
CHx turnon delay time tDR 5 18 25 µs VS = 24 V, RL = 48 Ω; 50% of EN to 10% of VOUT 13
CHx PWM accuracy - average load current ΔPWM -20 20 % 200-µs enable pulse, VS = 24 V, RL = 48 Ω, F = fmax 13
On-resistance (includes MOSFET and package), TJ = 25°C RON 72 mΩ 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 = 200 mA, TJ = 25°C 9
On-resistance (includes MOSFET and package), TJ = 125°C RON 110 mΩ 10 V ≤ VS ≤ 36 V, IOUT1 = IOUT2 = 200 mA, TJ = 125°C 9
Continuous load current, per channel ILNOM 1.6 A All channels enabled, TAMB = 85°C 9
Leakage current from OUT to GND in OFF state IOUT,LEAKX 40 µA Vs = VOUT < 36 V, switch and all diagnostics disabled, measured into the OUTx pin 9
Thermal resistance, junction-to-ambient RθJA 25.4 °C/W RHA (VQFN), 40 pins 8
Thermal resistance, junction-to-case (top) RθJC(top) 15.8 °C/W RHA (VQFN), 40 pins 8
Thermal resistance, junction-to-board RθJB 7.6 °C/W RHA (VQFN), 40 pins 8
Junction-to-top characterization parameter ψJT 0.2 °C/W RHA (VQFN), 40 pins 8
Junction-to-board characterization parameter ψJB 7.6 °C/W RHA (VQFN), 40 pins 8
Thermal resistance, junction-to-case (bottom) RθJC(bot) 0.6 °C/W RHA (VQFN), 40 pins 8
Continuous supply voltage, VVS to IC_GND VVS -0.3 40 V 7
Maximum transient (< 1 ms) voltage at supply pin, during ON state VVS -0.3 60 V During ON state, < 1 ms 7
VOUT voltage to IC_GND VOUT -30 V 7
VDS voltage VDS -0.7 39 V 7
Low voltage supply pin voltage, VDD VDD -0.3 7 V 7
Digital input pin voltages VDIG -0.3 7 V 7
LED drive pin voltage VLED_OUT -0.3 7 V 7
Analog pin voltage REG_EN -0.3 7 V 7
Sense pin voltage VSNS -0.3 7 V 7
FLT pin voltage VFLT -0.3 7 V 7
Reverse ground current IGND -50 mA VS < 0 V 7
Maximum junction temperature TJ 150 °C 7
Storage temperature Tstg -65 150 °C 7
Nominal supply voltage VS_OPMAX 12 36 V 7
Low voltage supply voltages VDD 3 5.5 V 7
All digital input pin voltage VDIG -0.3 5.5 V 7
FLT pin voltage VFLT -0.3 5.5 V 7
LED_OUTx pin voltage VLED_OUTx -0.3 5.5 V 7
REG_EN pin voltage VANA -0.3 5 V 7
SNS, ADDCFG pin voltage VANA -0.3 5 V 7
Operating free-air temperature TA -40 125 °C 8

CAD (KiCad official)

  • Symbol: TPS274C65ASHRHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: tps274c65ashrhar-etched.step / tps274c65ashrhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps274c65ashrhar.step / tps274c65ashrhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (92 pp, sha256 5e68c3837ef2ef8c, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF