TPS27081ADDCR

{
 "schema": "adom.pads/1",
 "slug": "tps27081addcr",
 "footprint": "SOT-23-6",
 "generated_from": {
  "footprint": "SOT-23-6@sha256:f341c73aac9dcb55",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -1.1375,
   -0.95
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOT-23-6@sha256:f341c73aac9dcb55"
 },
 "pad_count": 6,
 "symbol_pins": [
  "1",
  "2",
  "3",
  "4",
  "5",
  "6"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    -0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "R2",
   "type": "output",
   "description": "Source terminal of internal NMOS (Q2). Connect to system GND directly, or through an external slew-rate control resistor R2 to shape the ON/OFF transition and limit inrush current on CL.",
   "is_pin1": true,
   "source": {
    "geometry": "SOT-23-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "VOUT",
   "type": "power_out",
   "description": "Drain terminal of the power PFET (Q1); switched output to the load. Pins 2 and 3 are internally the same VOUT node; connect a slew-control capacitor CL between VOUT and R1/C1 (pin 6) if needed.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -1.1375,
    0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "VOUT",
   "type": "power_out",
   "description": "Drain terminal of the power PFET (Q1); switched output to the load. Tie pins 2 and 3 together on the board to share the full 3-A continuous / 9.5-A pulsed drain current.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.1375,
    0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "VIN",
   "type": "power_in",
   "description": "Source terminal of the power PFET (Q1). Supply input, 1.2 V to 8 V (abs max 8 V vs R2). Connect a pull-up resistor R1 between VIN and the R1/C1 gate node (pin 6).",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.1375,
    0.0
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "ON/OFF",
   "type": "input",
   "description": "Active-high enable input for the load switch; VIH >= 1 V, VIL <= 0.3 V, abs max 8 V. When driven by a high-impedance driver, connect an external pull-down resistor to GND to define the off state.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    1.1375,
    -0.95
   ],
   "rot": 0.0,
   "size": [
    1.325,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "R1/C1",
   "type": "passive",
   "description": "Gate terminal of the power PFET (Q1) and drain of the control NMOS (Q2). Connect the R1 pull-up resistor from VIN to this pin, and (optionally) a slew-shaping capacitor C1 between this pin and VOUT to control turn-on/turn-off dV/dt and inrush current.",
   "is_pin1": false,
   "source": {
    "geometry": "SOT-23-6.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}