component
TPS26636PWPT
Public Made by Adomby adom
Texas Instruments Power Management Specialized - PMIC, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS26636PWPT
Texas Instruments · Power Management Specialized - PMIC · HTSSOP-20-EP
TPS26636PWPT from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power input that connects to the drain of the internal 31 mΩ FET; IN and IN_SYS are specified for 4.5 V to 60 V operation. |
| 2 | IN | power_in | Power input that connects to the drain of the internal FET; IN and IN_SYS are specified for 4.5 V to 60 V operation. |
| 3 | IN | power_in | Power input (name cell blank in Table 5-1; assigned IN from Figure 5-4 and the pin-count pattern) connecting to the drain of the internal FET; do not leave any IN pin unconnected. |
| 4 | B_GATE | output | Blocking FET gate driver output; connect to the GATE of the external N-channel FET and leave floating if no external FET is used, with B_GATE to IN_SYS limited to 14 V. |
| 5 | DRV | output | Blocking FET fast pulldown switch drive; connect to the GATE of the external pulldown switch and leave floating if no external N-FET is used, with DRV to IN_SYS limited to 20 V. |
| 6 | IN_SYS | power_in | Power input and supply voltage of the device; connect to the source of the blocking FET when used, or short to IN if no blocking FET is used, with a minimum 0.1 µF capacitor across IN_SYS and GND. |
| 7 | UVLO | input | Input for the programmable undervoltage lockout threshold; an undervoltage event turns off the internal FET and asserts FLT, and connecting UVLO to GND selects the internal default threshold. |
| 8 | PLIM | input | Input for the programmable output power limit on TPS26636 (PLIM replaces OVP on this variant); connect a resistor from PLIM to GND to set the limit, or connect PLIM directly to GND to disable the feature. |
| 9 | GND | power_in | Connect to system ground; the PowerPAD must also be tied to the GND plane for heat sinking and must not be the only GND connection. |
| 10 | dVdT | bidirectional | A capacitor from this pin to GND sets the output voltage slew rate during hot plug-in and inrush control. |
| 11 | ILIM | bidirectional | A resistor from this pin to GND sets the overload and short-circuit current limit, with ILIM resistance specified from 3 kΩ to 30 kΩ; the FET turns off if ILIM is shorted or open to GND. |
| 12 | MODE | input | Mode selection pin for overload fault response (auto-retry or latch-off), with a recommended operating range of 0 V to 4 V. |
| 13 | SHDN | input | Shutdown pin; pulling it below 0.8 V enters low-power shutdown, cycling it resets a latched-off device, and it must be pulled up to at least 2 V to enable the device, with a recommended range of 0 V to 5 V. |
| 14 | IMON | output | Analog current monitor output that sources a current proportional to load current (27.9 µA/A typical) and must not exceed 4 V when converted by a resistor to GND; leave floating if unused and do not add a bypass capacitor. |
| 15 | FLT | output | Open-drain active-low fault indicator for undervoltage, overvoltage, overload, power limiting, reverse current, ILIM short and thermal shutdown; leave floating or connect to GND if unused, with a recommended range of 0 V to 60 V. |
| 16 | PGTH | input | PGOOD comparator input; PGOOD goes high when PGTH crosses the V(PGTHR) threshold, with an absolute maximum of 67 V. |
| 17 | PGOOD | output | Active-high power-good output that goes low when PGTH falls to V(PGTHF), with a maximum sink current of 10 mA; connect to GND or leave floating if unused. |
| 18 | OUT | power_out | Power output of the device, specified for 0 V to 60 V at the recommended operating conditions; do not leave OUT pins unconnected. |
| 19 | OUT | power_out | Power output of the device, specified for 0 V to 60 V at the recommended operating conditions; do not leave OUT pins unconnected. |
| 20 | OUT | power_out | Power output of the device (name cell blank in Table 5-1; assigned OUT from Figure 5-4 and the pin-count pattern); do not leave OUT pins unconnected. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
TPS26636PWPT - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tps26636pwpt-etched.step/tps26636pwpt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps26636pwpt.step/tps26636pwpt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
63ce6e9453e4499b, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).