# TPS26635RGET

**Texas Instruments** · Surge Protection Devices (SPDs) · VQFN-24(4x4)

TPS26635RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power input that connects to the DRAIN of the internal FET. |
| 2 | IN | power_in | Power input that connects to the DRAIN of the internal FET. |
| 3 | B_GATE | output | Blocking FET gate driver output; connect to the GATE of the external N-FET, or leave floating if no external FET is used. |
| 4 | DRV | output | Blocking FET fast pulldown switch drive; connect to the GATE of the external pulldown switch, and leave floating if no external N-FET is used. |
| 5 | IN_SYS | power_in | Power input and supply voltage of the device; connect to the source of the blocking FET when used, or short to IN if no blocking FET is used. |
| 6 | UVLO | input | Input for the programmable undervoltage lockout threshold; an undervoltage event turns off the internal FET and asserts FLT, and connecting to GND selects the internal default threshold. |
| 7 | PLIM | input | Input for the output power limiting threshold; a resistor from PLIM to GND sets the limit (60.4 kΩ to 150 kΩ), and connecting PLIM to GND disables the feature. |
| 8 | GND | power_in | Connect GND to system ground. |
| 9 | dVdT | bidirectional | A capacitor from this pin to GND sets the output voltage slew rate. |
| 10 | ILIM | bidirectional | A resistor from this pin to GND sets the overload and short-circuit current limit (3 kΩ to 30 kΩ). |
| 11 | MODE | input | Mode selection pin for overload fault response, with a recommended operating voltage of 0 V to 4 V. |
| 12 | SHDN | input | Shutdown pin; pulling it below the 0.8 V threshold enters low-power shutdown, cycling it resets a latched-off device, and the recommended range is 0 V to 5 V. |
| 13 | IMON | output | Analog current monitor output that sources a scaled-down ratio of FET current (27.9 µA/A typical); a resistor to GND converts it to voltage, limited to 4 V, and it should be left floating if unused. |
| 14 | FLT | output | Open-drain fault event indicator; leave floating or connect to GND if unused. |
| 15 | PGTH | input | PGOOD comparator input. |
| 16 | PGOOD | output | Active-high power-good output that goes high when PGTH crosses V(PGTHR) and goes low when V(PGTH) reaches V(PGTHF); leave floating or connect to GND if unused. |
| 17 | OUT | power_out | Power output of the device; OUT pins must not be left unconnected. |
| 18 | OUT | power_out | Power output of the device; OUT pins must not be left unconnected. |
| 19 | N.C. | unconnected | No connect. |
| 20 | N.C. | unconnected | No connect. |
| 21 | N.C. | unconnected | No connect. |
| 22 | N.C. | unconnected | No connect. |
| 23 | N.C. | unconnected | No connect. |
| 24 | N.C. | unconnected | No connect. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Circuit Protection |
| Pins | 25 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating input voltage | V(IN_SYS) | 4.5 |  | 60 | V |  | 6 |
| Supply current, enabled | IQ(ON) |  | 1.38 | 1.7 | mA | Enabled: V(SHDN) = 2 V | 6 |
| Supply current, shutdown | IQ(OFF) |  | 21 | 60 | µA | V(SHDN) = 0 V | 6 |
| Ground current during reverse polarity | I(GND) |  | 144 | 200 | µA | V(IN_SYS) = -24V, V(IN) = Floating, V(OUT) = 0 V | 6 |
| Over voltage clamp (TPS26635) | V(OVC) | 35.7 | 36.6 | 39 | V | TPS26635 and TPS26636, V(IN_SYS) > 40 V, I(OUT) = 1 mA | 6 |
| Factory set V(IN_SYS) undervoltage trip level, rising | V(INSYS_UVLO) | 15.1 | 15.46 | 15.9 | V | V(IN_SYS) rising, V(UVLO) = 0 V | 6 |
| Factory set V(IN_SYS) undervoltage trip level, falling | V(INSYS_UVLO) | 14 | 14.47 | 15.1 | V | V(IN_SYS) falling, V(UVLO) = 0 V | 6 |
| Internal UVLO select threshold | V(SEL_UVLO) | 180 | 210 | 240 | mV |  | 6 |
| UVLO threshold voltage, rising | V(UVLOR) | 1.176 | 1.2 | 1.224 | V |  | 6 |
| UVLO threshold voltage, falling | V(UVLOF) | 1.09 | 1.122 | 1.15 | V |  | 6 |
| UVLO input leakage current | I(UVLO) | -150 | 8 | 150 | nA | 0 V ≤ V(UVLO) ≤ 60 V | 6 |
| Overload current limit | I(OL) | 0.54 | 0.6 | 0.66 | A | R(ILIM) = 30 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Overload current limit | I(OL) | 1.84 | 2 | 2.16 | A | R(ILIM) = 9 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Overload current limit | I(OL) | 4.185 | 4.5 | 4.815 | A | R(ILIM) = 4.02 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Overload current limit | I(OL) | 5.58 | 6 | 6.42 | A | R(ILIM) = 3 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Power limit feature select threshold | V(SEL_PLIM) | 160 | 217 | 240 | mV |  | 7 |
| PLIM sourcing current | I(PLIM) | 4.4 | 5.02 | 5.6 | µA | V(PLIM) = 0 V | 7 |
| Max output power | P(PLIM) | 94 | 100 | 106 | W | R(PLIM) = 100 kΩ | 7 |
| Max output power | P(PLIM) | 141.9 | 151 | 160.1 | W | R(PLIM) = 150 kΩ (1) | 7 |
| B_GATE clamp voltage | V(B_GATE) | 8.3 | 10.23 | 14 | V | V(B_GATE), V(IN_SYS) | 7 |
| Blocking FET gate drive current | I(B_GATE) | 16 | 19.4 | 23 | µA | V(B_GATE), V(IN_SYS) = 1 V | 7 |
| B_GATE pull down resistance | Rpd_BGATE | 800 | 1010 | 1200 | kΩ |  | 7 |
| DRV logic high level | V(DRV_OH) | 3 | 4.25 | 5.2 | V | V(DRV), V(IN_SYS), C(DRV) ≤ 50 pF | 7 |
| IN to OUT total ON resistance, TJ = 25°C | RON | 26 | 30.44 | 34.5 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 25°C | 7 |
| IN to OUT total ON resistance, TJ = 85°C | RON |  | 33 | 45 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 85°C | 7 |
| IN to OUT total ON resistance, -40°C to +125°C | RON | 19 | 30.44 | 53 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, -40°C ≤ TJ ≤ +125°C | 7 |
| V(IN_SYS), V(OUT) threshold for reverse protection comparator, rising | V(REVTH) | -20 | -15 | -9 | mV |  | 7 |
| V(IN_SYS), V(OUT) threshold for reverse protection comparator, falling | V(FWDTH) | 45 | 57 | 67 | mV |  | 7 |
| dVdT charging current | I(dVdT) | 1.775 | 2 | 2.225 | µA | V(dVdT) = 0 V | 7 |
| dVdT to OUT gain | GAIN(dVdT) | 23.5 | 25 | 26 | V/V |  | 7 |
| dVdT maximum capacitor voltage | V(dVdTmax) | 3.8 | 4.17 | 4.75 | V |  | 7 |
| dVdT discharging resistance | R(dVdT) | 10 | 16.6 | 26.6 | Ω |  | 7 |
| SHDN open circuit voltage | V(SHDN) | 2.48 | 2.7 | 3.3 | V | I(SHDN) = 0.1 µA | 7 |
| Thermal regulation timeout | t(Treg_timeout) | 2.3 | 2.54 | 2.9 | s |  | 10 |
| Input voltage (IN_SYS, IN) | V(IN_SYS), V(IN) | 4.5 |  | 60 | V |  | 5 |
| Input voltage (OUT, UVLO, PGTH, PGOOD, FLT) | V(OUT), V(UVLO), V(PGTH), V(PGOOD), V(FLT) | 0 |  | 60 | V |  | 5 |
| Input voltage (OVP, dVdT, IMON, MODE), OVP pin not used on TPS26635 |  | 0 |  | 4 | V |  | 5 |
| Input voltage (SHDN) | V(SHDN) | 0 |  | 5 | V |  | 5 |
| ILIM resistance | R(ILIM) | 3 |  | 30 | kΩ |  | 5 |
| PLIM resistance | R(PLIM) | 60.4 |  | 150 | kΩ |  | 5 |
| Operating junction temperature | TJ | -40 | 25 | 125 | °C |  | 6 |
| Input voltage (IN_SYS) | V(IN_SYS) | -60 |  | 67 | V |  | 5 |
| Input voltage (IN_SYS), 10 ms transient | V(IN_SYS) | -60 |  | 75 | V | 10ms transient, TA = 25 ℃ | 5 |
| Input voltage (IN, OUT, UVLO, FLT, PGOOD, PGTH) | V(IN), V(OUT), V(UVLO), V(FLT), V(PGOOD), V(PGTH) | -0.3 |  | 67 | V |  | 5 |
| Input voltage (IN), 10 ms transient | V(IN) | -0.3 |  | 75 | V | 10ms transient, TA = 25 ℃ | 5 |
| Input voltage (BGATE) | V(B_GATE) | -60 |  | 81 | V |  | 5 |
| Input voltage (BGATE, IN_SYS) | V(B_GATE), V(IN_SYS) | -0.3 |  | 14 | V |  | 5 |
| Input voltage (DRV) | V(DRV) | -60 |  | 72 | V |  | 5 |
| Input voltage (DRV, IN_SYS) | V(DRV), V(IN_SYS) | -0.3 |  | 20 | V |  | 5 |
| Input voltage (OVP, dVdT, IMON, MODE, SHDN, ILIM, PLIM) |  | -0.3 |  | 5.5 | V |  | 5 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 5 |
| Transient junction temperature | TJ | -65 |  |  | °C | Maximum printed as T(TSD), not a numeric value | 5 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 31.4 |  | °C/W | RGE (VSON) 24 pins | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 23.2 |  | °C/W | RGE (VSON) 24 pins | 6 |
| Junction-to-board thermal resistance | RθJB |  | 10.2 |  | °C/W | RGE (VSON) 24 pins | 6 |
| Junction-to-top characterization parameter | ΨJT |  | 0.3 |  | °C/W | RGE (VSON) 24 pins | 6 |
| Junction-to-board characterization parameter | ΨJB |  | 10.2 |  | °C/W | RGE (VSON) 24 pins | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2.8 |  | °C/W | RGE (VSON) 24 pins | 6 |

## CAD (KiCad official)

- Symbol: `TPS26635RGET`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files: `tps26635rget-etched.step` / `tps26635rget-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps26635rget.step` / `tps26635rget.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tps2663) (60 pp, sha256 `63ce6e9453e4499b`, retrieved 2026-10-21, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tps26635rget-datasheet.pdf)