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TPS26633PWPT

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Texas Instruments Surge Protection Devices (SPDs), HTSSOP-20. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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TPS26633PWPT

Texas Instruments · Surge Protection Devices (SPDs) · HTSSOP-20

TPS26633PWPT from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PLIM input Programmable output power limiting threshold input; connect resistor to GND to set power limit or connect to GND if feature not used.
2 B_GATE output Blocking FET gate driver output for external N-channel FET; connect to FET gate for reverse polarity protection or leave floating if not used.
3 IN power_in Power input connecting to the internal FET drain; supports multiple pin connections for current distribution.
4 IN_SYS power_in Power input and device supply voltage; connect to external FET source or short to IN if blocking FET not used.
5 IN power_in Power input connecting to the internal FET drain; supports multiple pin connections for current distribution.
6 SHDN input Shutdown input; pull below 0.8V to enter low-power shutdown mode or cycle to reset latched-off faults.
7 OUT power_out Power output of the device; supports multiple pin connections for current distribution.
8 OUT power_out Power output of the device; supports multiple pin connections for current distribution.
9 GND power_in Ground connection; connect to system ground with minimum 0.1-µF bypass capacitor to IN_SYS.
10 PGTH input PGOOD comparator threshold input for power good signal monitoring.
11 dVdT bidirectional Output voltage slew rate control input/output; connect capacitor to GND (10 nF typical) to set inrush current limit.
12 ILIM bidirectional Overload and short-circuit current limit input/output; connect resistor to GND (3 kΩ to 30 kΩ) to set current limit per equation I(OL) = 18/R(ILIM).
13 PGOOD output Power good active-high open-drain output; goes high when PGTH exceeds rising threshold and internal FET enhanced, low at falling threshold.
14 MODE input Fault response mode selection input; open for latch-off or shorted to GND for auto-retry on overload.
15 IN power_in Power input connecting to the internal FET drain; supports multiple pin connections for current distribution.
16 DRV output Blocking FET fast pulldown switch drive output; connect to external pulldown switch gate or leave floating if not used.
17 UVLO input Programmable undervoltage lockout threshold input; connect to GND for internal default 3.1V threshold.
18 IMON output Analog current monitor output sourcing 27.9 µA/A of load current; connect resistor to GND to convert to proportional voltage.
19 FLT output Fault event indicator open-drain output asserting low on undervoltage, overvoltage, overload, reverse current, ILIM fault, or thermal shutdown.
20 OUT power_out Power output of the device; supports multiple pin connections for current distribution.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20
Category Circuit Protection
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
IN_SYS input voltage IN_SYS -60 67 V 5
IN_SYS input voltage (10 ms transient) IN_SYS -60 75 V TA = 25 °C 5
IN, OUT, UVLO, FLT, PGOOD, PGTH voltage IN, OUT, UVLO, FLT, PGOOD, PGTH -0.3 67 V 5
IN (10 ms transient) IN -0.3 75 V TA = 25 °C 5
IN_SYS, OUT (10 ms transient) with blocking FET IN_SYS, OUT -85 V 10 ms transient, with a Blocking FET 5
BGATE voltage BGATE -60 81 V 5
BGATE, IN_SYS voltage BGATE, IN_SYS -0.3 14 V 5
DRV voltage DRV -60 72 V 5
DRV, IN_SYS voltage DRV, IN_SYS -0.3 20 V 5
OVP, dVdT, IMON, MODE, SHDN, ILIM, PLIM voltage OVP, dVdT, IMON, MODE, SHDN, ILIM, PLIM -0.3 5.5 V 5
IFLT, IdVdT, IPGOOD sink current IFLT, IdVdT, IPGOOD 10 mA Sink current 5
Operating junction temperature (absolute maximum) TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Input voltage (IN_SYS, IN) IN_SYS, IN 4.5 60 V 5
Voltage (OUT, UVLO, PGTH, PGOOD, FLT) OUT, UVLO, PGTH, PGOOD, FLT 0 60 V 5
Voltage (OVP, dVdT, IMON, MODE) OVP, dVdT, IMON, MODE 0 4 V 5
Voltage (SHDN) SHDN 0 5 V 5
ILIM resistance R(ILIM) 3 30 kΩ 5
IMON resistance R(IMON) 1 kΩ 5
PLIM resistance R(PLIM) 60.4 150 kΩ 5
External capacitance (IN, IN_SYS, OUT) C(IN), C(IN_SYS), C(OUT) 0.1 µF 5
dVdT external capacitance C(dVdT) 10 nF 5
Operating junction temperature (recommended) TJ -40 25 125 °C 6
Operating input voltage V(IN_SYS) 4.5 60 V 6
Supply current, enabled IQ(ON) 1.38 1.7 mA Enabled: V(SHDN) = 2 V 6
Supply current, shutdown IQ(OFF) 21 60 µA V(SHDN) = 0 V 6
Ground current during reverse polarity I(GND) 144 200 µA V(IN_SYS) = -24V, V(IN) = Floating, V(OUT) = 0 V 6
Over voltage clamp V(OVC) 32 32.8 35 V TPS26632 and TPS26633, V(IN_SYS) > 35 V, I(OUT) = 1 mA 6
Factory set V(IN_SYS) undervoltage trip level, rising V(INSYS_UVLO) 15.1 15.46 15.9 V V(IN_SYS) rising, V(UVLO) = 0 V 6
Factory set V(IN_SYS) undervoltage trip level, falling V(INSYS_UVLO) 14 14.47 15.1 V V(IN_SYS) falling, V(UVLO) = 0 V 6
UVLO threshold voltage, rising V(UVLOR) 1.176 1.2 1.224 V 6
UVLO threshold voltage, falling V(UVLOF) 1.09 1.122 1.15 V 6
UVLO input leakage current I(UVLO) -150 8 150 nA 0 V ≤ V(UVLO) ≤ 60 V 6
Overload current limit I(OL) 0.54 0.6 0.66 A R(ILIM) = 30 kΩ, V(IN), V(OUT) = 1 V 7
Overload current limit I(OL) 1.84 2 2.16 A R(ILIM) = 9 kΩ, V(IN), V(OUT) = 1 V 7
Overload current limit I(OL) 4.185 4.5 4.815 A R(ILIM) = 4.02 kΩ, V(IN), V(OUT) = 1 V 7
Overload current limit I(OL) 5.58 6 6.42 A R(ILIM) = 3 kΩ, V(IN), V(OUT) = 1 V 7
PLIM sourcing current I(PLIM) 4.4 5.02 5.6 µA V(PLIM) = 0 V 7
Max output power P(PLIM) 94 100 106 W R(PLIM) = 100 kΩ 7
Max output power P(PLIM) 141.9 151 160.1 W R(PLIM) = 150 kΩ (1) 7
B_GATE clamp voltage V(B_GATE) 8.3 10.23 14 V V(B_GATE), V(IN_SYS) 7
Blocking FET gate drive current I(B_GATE) 16 19.4 23 µA V(B_GATE), V(IN_SYS) = 1 V 7
B_GATE pull down resistance Rpd_BGATE 800 1010 1200 kΩ 7
DRV logic high level V(DRV_OH) 3 4.25 5.2 V V(DRV), V(IN_SYS), C(DRV) ≤ 50 pF 7
IN to OUT total ON resistance, TJ = 25 °C RON 26 30.44 34.5 mΩ 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 25°C 7
IN to OUT total ON resistance, TJ = 85 °C RON 33 45 mΩ 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 85°C 7
IN to OUT total ON resistance, -40 °C ≤ TJ ≤ +125 °C RON 19 30.44 53 mΩ 0.6 A ≤ I(OUT) ≤ 6 A, -40°C ≤ TJ ≤ +125°C 7
OUT leakage during input supply brownout Ilkg(OUT) -100 µA V(IN_SYS) = 0 V, V(OUT) = 24 V, V(IN) = Floating, V(SHDN) = 2V, Sinking 7
V(IN_SYS), V(OUT) reverse protection threshold, rising V(REVTH) -20 -15 -9 mV 7
V(IN_SYS), V(OUT) reverse protection threshold, falling V(FWDTH) 45 57 67 mV 7
dVdT charging current I(dVdT) 1.775 2 2.225 µA V(dVdT) = 0 V 7
dVdT to OUT gain GAIN(dVdT) 23.5 25 26 V/V V(OUT) /V(dVdT) 7
dVdT maximum capacitor voltage V(dVdTmax) 3.8 4.17 4.75 V 7
dVdT discharging resistance R(dVdT) 10 16.6 26.6 Ω 7
SHDN open circuit voltage V(SHDN) 2.48 2.7 3.3 V I(SHDN) = 0.1 µA 7
SHDN threshold voltage for low IQ shutdown, falling V(SHUTF) 0.8 V 7
SHDN threshold rising V(SHUTR) 2 V 7
Thermal regulation timeout t(Treg_timeout) 2.3 2.54 2.9 s 10
Junction-to-ambient thermal resistance (PWP) RθJA 32.2 °C/W PWP (HTSSOP), 20 pins 6
Junction-to-case (bottom) thermal resistance (PWP) RθJC(bot) 3.6 °C/W PWP (HTSSOP), 20 pins 6

CAD (KiCad official)

  • Symbol: TPS26633PWPT
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps26633pwpt-etched.step / tps26633pwpt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps26633pwpt.step / tps26633pwpt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 63ce6e9453e4499b, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF