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TPS26633PWPR

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Texas Instruments Surge Protection Devices (SPDs), HTSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS26633PWPR

Texas Instruments · Surge Protection Devices (SPDs) · HTSSOP-20

TPS26633PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input that connects to the drain of the internal FET; recommended input voltage is 4.5 V to 60 V and the absolute maximum is 67 V.
2 IN power_in Power input that connects to the drain of the internal FET; recommended input voltage is 4.5 V to 60 V and the absolute maximum is 67 V.
3 IN power_in Power input that connects to the drain of the internal FET; recommended input voltage is 4.5 V to 60 V and the absolute maximum is 67 V.
4 B_GATE output Blocking FET gate driver output that connects to the GATE of the external N-channel FET; B_GATE to IN_SYS is limited to 14 V, and the pin should be left floating if no external FET is used.
5 DRV output Blocking FET fast pulldown switch drive that connects to the GATE of the external pulldown switch; DRV to IN_SYS is limited to 20 V, and the pin should be left floating if no external N-FET is used.
6 IN_SYS power_in Power input and supply voltage of the device, recommended 4.5 V to 60 V; connect to the FET source when an external blocking FET is used, or short to IN if it is not.
7 UVLO input Input for the programmable undervoltage lockout threshold; an undervoltage event turns off the internal FET and asserts FLT, and connecting UVLO to GND selects the internal default threshold.
8 PLIM input Input for the output power limit; connect a resistor from PLIM to GND (recommended 60.4 to 150 kΩ), or connect PLIM directly to GND to disable power limiting.
9 GND power_in Connect to system ground; the PowerPAD must be tied to the GND plane for heat sinking and must not be the only GND connection.
10 dVdT bidirectional A capacitor from this pin to GND sets the output voltage slew rate during hot plug-in and inrush control; the pin is limited to -0.3 V to 5.5 V.
11 ILIM bidirectional A resistor from this pin to GND sets the overload and short-circuit current limit, with a recommended resistance of 3 to 30 kΩ; the internal FET turns off if ILIM is shorted or open to GND.
12 MODE input Mode selection pin for the overload fault response (auto-retry or latch-off), with a recommended operating range of 0 V to 4 V.
13 SHDN input Shutdown pin; pulling it below the 0.8 V threshold enters low-power shutdown, and it must be pulled up to at least 2 V to enable the device, with a recommended range of 0 V to 5 V.
14 IMON output Analog current monitor output that sources a current scaled from the internal FET current; a resistor to GND converts it to voltage, the maximum IMON voltage is limited to 4 V, and no bypass capacitor should be used on this pin.
15 FLT output Open-drain fault indicator that asserts low for undervoltage, overvoltage, overload, power limiting, reverse current, ILIM short, and thermal shutdown; sink current is limited to 10 mA.
16 PGTH input PGOOD comparator input, with a recommended range of 0 V to 60 V; PGOOD goes high when PGTH crosses V(PGTHR) and goes low when PGTH falls to V(PGTHF).
17 PGOOD output Active-high power-good output that goes high when PGTH crosses V(PGTHR) and the internal FET is enhanced, and goes low when PGTH reaches V(PGTHF); sink current is limited to 10 mA.
18 OUT power_out Power output of the device, with a recommended operating voltage of 0 V to 60 V.
19 OUT power_out Power output of the device, with a recommended operating voltage of 0 V to 60 V.
20 OUT power_out Power output of the device, with a recommended operating voltage of 0 V to 60 V.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20
Category Circuit Protection
Pins 21

CAD (KiCad official)

  • Symbol: TPS26633PWPR
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps26633pwpr-etched.step / tps26633pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps26633pwpr.step / tps26633pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 63ce6e9453e4499b, retrieved 2026-10-10, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF