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TPS26631PWPR
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Texas Instruments Surge Protection Devices (SPDs), HTSSOP-20. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownTPS26631PWPR
Texas Instruments · Surge Protection Devices (SPDs) · HTSSOP-20
TPS26631PWPR from Texas Instruments, in a HTSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power input that connects to the DRAIN of the internal FET; the recommended IN_SYS and IN input voltage range is 4.5 V to 60 V. |
| 2 | IN | power_in | Power input that connects to the DRAIN of the internal FET; the recommended IN_SYS and IN input voltage range is 4.5 V to 60 V. |
| 3 | IN | power_in | Power input that connects to the DRAIN of the internal FET; the recommended IN_SYS and IN input voltage range is 4.5 V to 60 V. |
| 4 | B_GATE | output | Blocking FET gate driver output that connects to the GATE of the external N-FET; leave floating if no external FET is used. |
| 5 | DRV | output | Blocking FET fast pulldown switch drive that connects to the GATE of the external pulldown switch; leave floating if the external N-FET is not used. |
| 6 | IN_SYS | power_in | Power input and supply voltage of the device; connect to the source of the blocking FET when used, or short to IN when no blocking FET is used. |
| 7 | UVLO | input | Input for the programmable undervoltage lockout threshold; an undervoltage event turns off the internal FET and asserts FLT, and connecting UVLO to GND selects the internal default threshold. |
| 8 | OVP | input | Input for the programmable overvoltage protection threshold (TPS26630 and TPS26631 only); an overvoltage event turns off the internal FET and asserts FLT, and connecting OVP to GND selects the internal default threshold. |
| 9 | GND | power_in | Connect to system ground. |
| 10 | dVdT | bidirectional | A capacitor from this pin to GND sets the output voltage slew rate (see Hot Plug-In and InRush Current Control section). |
| 11 | ILIM | bidirectional | A resistor from this pin to GND sets the overload and short-circuit current limit; ILIM resistance is specified from 3 kΩ to 30 kΩ. |
| 12 | MODE | input | Mode selection pin for overload fault response; see the Device Functional Modes section. |
| 13 | SHDN | input | Shutdown pin; pulling SHDN low puts the device into low-power shutdown mode, and cycling SHDN resets a device latched off by a fault. |
| 14 | IMON | output | Analog current monitor output that sources a scaled-down ratio of the FET current; a resistor to GND converts it to a proportional voltage, and the pin should be left floating if unused. |
| 15 | FLT | output | Fault event indicator that is an open-drain output; leave floating or connect to GND if unused. |
| 16 | PGTH | input | PGOOD comparator input. |
| 17 | PGOOD | output | Active-high power-good output that goes high when PGTH crosses V(PGTHR) with the internal FET enhanced and goes low when PGTH falls to V(PGTHF); connect to GND or leave floating if unused. |
| 18 | OUT | power_out | Power output of the device. |
| 19 | OUT | power_out | Power output of the device. |
| 20 | N.C. | unconnected | No connect. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20 |
| Category | Circuit Protection |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IN_SYS input voltage | -60 | 67 | V | 5 | |||
| IN_SYS input voltage (10 ms transient) | -60 | 75 | V | 10 ms transient, TA = 25 ℃ | 5 | ||
| IN, OUT, UVLO, FLT, PGOOD, PGTH voltage | -0.3 | 67 | V | 5 | |||
| IN voltage (10 ms transient) | -0.3 | 75 | V | 10 ms transient, TA = 25 ℃ | 5 | ||
| IN_SYS, OUT voltage (blocking FET) | -85 | V | 10 ms transient, with a Blocking FET | 5 | |||
| BGATE voltage | -60 | 81 | V | 5 | |||
| BGATE, IN_SYS voltage | -0.3 | 14 | V | 5 | |||
| DRV voltage | -60 | 72 | V | 5 | |||
| DRV, IN_SYS voltage | -0.3 | 20 | V | 5 | |||
| OVP, dVdT, IMON, MODE, SHDN, ILIM, PLIM voltage | -0.3 | 5.5 | V | 5 | |||
| IFLT, IdVdT, IPGOOD sink current | IFLT | 10 | mA | 5 | |||
| Operating junction temperature TJ | TJ | -40 | 150 | °C | 5 | ||
| Transient junction temperature | -65 | °C | 5 | ||||
| Storage temperature Tstg | Tstg | -65 | 150 | °C | 5 | ||
| IN_SYS, IN input voltage | 4.5 | 60 | V | 5 | |||
| OUT, UVLO, PGTH, PGOOD, FLT voltage | 0 | 60 | V | 5 | |||
| OVP, dVdT, IMON, MODE voltage | 0 | 4 | V | 5 | |||
| SHDN voltage | 0 | 5 | V | 5 | |||
| ILIM resistance | R(ILIM) | 3 | 30 | kΩ | 5 | ||
| IMON resistance | R(IMON) | 1 | kΩ | 5 | |||
| IN, IN_SYS, OUT external capacitance | 0.1 | µF | 5 | ||||
| dVdT external capacitance | C(dVdT) | 10 | nF | 5 | |||
| Operating junction temperature TJ | TJ | -40 | 25 | 125 | °C | 6 | |
| IN_SYS operating input voltage | V(IN_SYS) | 4.5 | 60 | V | 6 | ||
| Supply current, enabled | IQ(ON) | 1.38 | 1.7 | mA | Enabled: V(SHDN) = 2 V | 6 | |
| Supply current, shutdown | IQ(OFF) | 21 | 60 | µA | V(SHDN) = 0 V | 6 | |
| Ground current during reverse polarity | I(GND) | 144 | 200 | µA | V(IN_SYS) = -24V, V(IN) = Floating, V(OUT) = 0 V | 6 | |
| IN_SYS undervoltage trip level, rising | V(INSYS_UVLO) | 15.1 | 15.46 | 15.9 | V | V(IN_SYS) rising, V(UVLO) = 0 V | 6 |
| IN_SYS undervoltage trip level, falling | V(INSYS_UVLO) | 14 | 14.47 | 15.1 | V | V(IN_SYS) falling, V(UVLO) = 0 V | 6 |
| UVLO threshold voltage, rising | V(UVLOR) | 1.176 | 1.2 | 1.224 | V | 6 | |
| UVLO threshold voltage, falling | V(UVLOF) | 1.09 | 1.122 | 1.15 | V | 6 | |
| IN_SYS overvoltage trip level, rising | V(IN_SYS_OVP) | 33.2 | 34.33 | 35.4 | V | V(IN_SYS) rising, V(OVP) = 0 V | 6 |
| IN_SYS overvoltage trip level, falling | V(IN_SYS_OVP) | 32.7 | 33.89 | 35 | V | V(IN_SYS) falling, V(OVP) = 0 V | 6 |
| Over-voltage threshold voltage, rising | V(OVPR) | 1.176 | 1.2 | 1.224 | V | 6 | |
| Over-voltage threshold voltage, falling | V(OVPF) | 1.09 | 1.122 | 1.15 | V | 6 | |
| Overload current limit | I(OL) | 0.54 | 0.6 | 0.66 | A | R(ILIM) = 30 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Overload current limit | I(OL) | 1.84 | 2 | 2.16 | A | R(ILIM) = 9 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Overload current limit | I(OL) | 4.185 | 4.5 | 4.815 | A | R(ILIM) = 4.02 kΩ, V(IN), V(OUT) = 1 V | 7 |
| Overload current limit | I(OL) | 5.58 | 6 | 6.42 | A | R(ILIM) = 3 kΩ, V(IN), V(OUT) = 1 V | 7 |
| B_GATE clamp voltage | V(B_GATE) | 8.3 | 10.23 | 14 | V | V(B_GATE), V(IN_SYS) | 7 |
| Blocking FET gate drive current | I(B_GATE) | 16 | 19.4 | 23 | µA | V(B_GATE), V(IN_SYS) = 1 V | 7 |
| B_GATE pull down resistance | Rpd_BGATE | 800 | 1010 | 1200 | kΩ | 7 | |
| DRV logic high level | V(DRV_OH) | 3 | 4.25 | 5.2 | V | V(DRV), V(IN_SYS), C(DRV) ≤ 50 pF | 7 |
| IN to OUT total ON resistance, TJ = 25 °C | RON | 26 | 30.44 | 34.5 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 25°C | 7 |
| IN to OUT total ON resistance, TJ = 85 °C | RON | 33 | 45 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, TJ = 85°C | 7 | |
| IN to OUT total ON resistance, -40 °C to +125 °C | RON | 19 | 30.44 | 53 | mΩ | 0.6 A ≤ I(OUT) ≤ 6 A, -40°C ≤ TJ ≤ +125°C | 7 |
| OUT leakage during input supply brownout | Ilkg(OUT) | -100 | µA | V(IN_SYS) = 0 V, V(OUT) = 24 V, V(IN) = Floating, V(SHDN) = 2V, Sinking | 7 | ||
| V(IN_SYS), V(OUT) reverse protection threshold, rising | V(REVTH) | -20 | -15 | -9 | mV | 7 | |
| V(IN_SYS), V(OUT) reverse protection threshold, falling | V(FWDTH) | 45 | 57 | 67 | mV | 7 | |
| dVdT charging current | I(dVdT) | 1.775 | 2 | 2.225 | µA | V(dVdT) = 0 V | 7 |
| dVdT to OUT gain | GAIN(dVdT) | 23.5 | 25 | 26 | V/V | 7 | |
| Open circuit voltage, SHDN | V(SHDN) | 2.48 | 2.7 | 3.3 | V | I(SHDN) = 0.1 µA | 7 |
| SHDN leakage current | I(SHDN) | -10 | µA | V(SHDN) = 0 V | 7 | ||
| Thermal regulation timeout | t(Treg_timeout) | 2.3 | 2.54 | 2.9 | s | 10 | |
| Junction-to-ambient thermal resistance (PWP, HTSSOP-20) | RθJA | 32.2 | °C/W | 6 | |||
| Junction-to-case (top) thermal resistance (PWP) | RθJC(top) | 23.4 | °C/W | 6 | |||
| Junction-to-board thermal resistance (PWP) | RθJB | 10 | °C/W | 6 | |||
| Junction-to-top characterization parameter (PWP) | ΨJT | 0.3 | °C/W | 6 | |||
| Junction-to-board characterization parameter (PWP) | ΨJB | 9.9 | °C/W | 6 | |||
| Junction-to-case (bottom) thermal resistance (PWP) | RθJC(bot) | 3.6 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
TPS26631PWPR - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
tps26631pwpr-etched.step/tps26631pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps26631pwpr.step/tps26631pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
63ce6e9453e4499b, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).