Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

TPS26400RHFR

Texas Instruments · Surge Suppressors · VQFN-24(4x5)

TPS26400RHFR from Texas Instruments, in a VQFN-24(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 N.C unconnected No connect.
2 N.C unconnected No connect.
3 N.C unconnected No connect.
4 N.C unconnected No connect.
5 N.C unconnected No connect.
6 N.C unconnected No connect.
7 N.C unconnected No connect.
8 IN power_in Power input and supply voltage of the device; all IN pins must be connected together, recommended range 4.2 V to 42 V.
9 IN power_in Power input and supply voltage of the device; all IN pins must be connected together, recommended range 4.2 V to 42 V.
10 UVLO input Input for setting the programmable undervoltage lockout threshold; an undervoltage event turns off the internal FET and asserts FLT, and connecting UVLO to RTN selects the internal default threshold.
11 N.C unconnected No connect.
12 OVP input Input for setting the programmable overvoltage protection threshold; an overvoltage event turns off the internal FET and asserts FLT, and connecting OVP to RTN selects the factory-set V(IN) overvoltage trip level.
13 MODE input Mode selection pin for overload fault response: open = circuit breaker with auto-retry, shorted to RTN = active current limiting with auto-retry, 402-kΩ to RTN = current limiting with latch-off.
14 SHDN input Shutdown pin; pulling it low enters low-power shutdown mode (about 20 μA typical), and cycling it resets a device latched off by a fault.
15 RTN power_in Reference for device internal control circuits; connect R(ILIM), C(dVdT), R(IMON), R(MODE), UVLO and OVP resistors to it and do not short it to GND.
16 N.C unconnected No connect.
17 GND power_in Connect GND to system ground.
18 IMON output Analog current monitor output sourcing a scaled-down ratio of the internal FET current (78.4 μA/A typical), converted to voltage by a resistor to RTN; leave floating if unused.
19 ILIM bidirectional A resistor from this pin to RTN sets the overload and short-circuit current limit (recommended 5.36 kΩ to 120 kΩ).
20 dVdT bidirectional A capacitor from this pin to RTN sets the output voltage slew rate; when left floating the internal ramp rate is 23.9 V/1.6 ms.
21 N.C unconnected No connect.
22 FLT output Fault event indicator, open-drain output; leave floating if unused.
23 OUT power_out Power output of the device; all OUT pins must be connected together and to the load.
24 OUT power_out Power output of the device; all OUT pins must be connected together and to the load.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x5)
Category TVS/Fuse/Board Level Protection
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating input voltage V(IN) 4.2 42 V 7
Internal POR threshold, rising V(PORR) 3.9 4 4.1 V 7
Internal POR hysteresis V(PORHys) 250 275 300 mV 7
Supply current enabled IQ(ON) 190 300 390 µA V(SHDN) = 2 V 7
Supply current shutdown IQ(OFF) 11 20 33 µA V(SHDN) = 0 V 7
Reverse input supply current I(VINR) 66 µA V(IN) = -42 V, V(OUT) = 0 V 7
Factory set UVLO trip level, rising V(IN_UVLO) 14.25 14.9 15.75 V V(IN) rising, V(UVLO) = 0 V 7
Factory set UVLO trip level, falling V(IN_UVLO) 13.25 13.8 14.75 V V(IN) falling, V(UVLO) = 0 V 7
Internal UVLO select threshold V(SEL_UVLO) 180 200 240 mV 7
UVLO threshold voltage, rising V(UVLOR) 1.175 1.19 1.225 V 7
UVLO threshold voltage, falling V(UVLOF) 1.08 1.1 1.125 V 7
UVLO input leakage current I(UVLO) -100 0 100 nA 0 V ≤ V(UVLO) ≤ 42 V 7
SHDN output voltage V(SHDN) 2 2.7 3.4 V I(SHDN) = 0.1 µA 7
SHDN threshold for low IQ shutdown, falling V(SHUTF) 0.55 0.76 0.94 V 7
SHDN leakage current I(SHDN) -10 µA V(SHDN) = 0.4 V 7
Factory set OVP trip level, rising V(IN_OVP) 31 32.6 34 V V(IN) rising, V(OVP) = 0 V 7
Factory set OVP trip level, falling V(IN_OVP) 28.5 30.3 31.5 V V(IN) falling, V(OVP) = 0 V 7
Internal OVP select threshold V(SEL_OVP) 180 200 240 mV 7
Overvoltage threshold voltage, rising V(OVPR) 1.17 1.19 1.225 V 7
Overvoltage threshold, falling V(OVPF) 1.085 1.1 1.125 V 7
OVP input leakage current I(OVP) -100 0 100 nA 0 V ≤ V(OVP) ≤ 4 V 7
dVdT charging current I(dVdT) 4 4.7 5.5 µA V(dVdT) = 0 V 7
dVdT discharging resistance R(dVdT) 14 Ω V(SHDN) = 0 V, with I(dVdT) = 10 mA sinking 7
dVdT to OUT gain GAIN(dVdT) 23.75 24.6 25.5 V/V V(OUT)/V(dVdT) 7
ILIM bias voltage V(ILIM) 1 V 7
Overload current limit I(OL) 0.085 0.1 0.115 A R(ILIM) = 120 kΩ, V(IN), V(OUT) = 1 V 7
Overload current limit I(OL) 0.95 1 1.05 A R(ILIM) = 12 kΩ, V(IN), V(OUT) = 1 V 7
Overload current limit I(OL) 1.425 1.5 1.575 A R(ILIM) = 8 kΩ, V(IN), V(OUT) = 1 V 7
Overload current limit I(OL) 2.11 2.23 2.35 A R(ILIM) = 5.36 kΩ, V(IN), V(OUT) = 1 V 7
Open resistor current limit I(OL_R-OPEN) 0.055 A R(ILIM) = OPEN, open resistor current limit (single point failure test: UL60950) 7
Shorted resistor current limit I(OL_R-SHORT) 0.095 A R(ILIM) = SHORT, shorted resistor current limit (single point failure test: UL60950) 7
Circuit breaker detection threshold I(CB) 0.045 0.073 0.11 A R(ILIM) = 120 kΩ, MODE = open 7
Circuit breaker detection threshold I(CB) 2 2.21 2.4 A R(ILIM) = 5.36 kΩ, MODE = open 7
Short-circuit current limit I(SCL) 0.08 0.1 0.12 A R(ILIM) = 120 kΩ, V(IN), V(OUT) = 5 V 8
Short-circuit current limit I(SCL) 1.425 1.5 1.575 A R(ILIM) = 8 kΩ, V(IN), V(OUT) = 5 V 8
Short-circuit current limit I(SCL) 2.11 2.23 2.35 A R(ILIM) = 5.36 kΩ, V(IN), V(OUT) = 5 V 8
Current monitor gain GAIN(IMON) 72 78.28 85 µA/A I(IMON): I(OUT), 0.1 A ≤ I(OUT) ≤ 2 A 8
IN to OUT total ON resistance RON 140 150 160 mΩ 0.1 A ≤ I(OUT) ≤ 2 A, TJ = 25°C 8
IN to OUT total ON resistance RON 210 mΩ 0.1 A ≤ I(OUT) ≤ 2 A, TJ = 85°C 8
IN to OUT total ON resistance RON 80 150 250 mΩ 0.1 A ≤ I(OUT) ≤ 2 A, -40°C ≤ TJ ≤ +125°C 8
OUT leakage current in Off state Ilkg(OUT) 12 µA V(IN) = 42 V, V(SHDN)= 0 V, V(OUT) = 0 V, sourcing 8
OUT leakage current in Off state Ilkg(OUT) 11 µA V(IN) = 0 V, V(SHDN)= 0 V, V(OUT) = 24 V, sinking 8
OUT leakage current in Off state Ilkg(OUT) 50 µA V(IN) = -42 V, V(SHDN)= 0 V, V(OUT) = 0 V, sinking 8
Reverse protection comparator threshold, falling V(REVTH) -15 -10 -5 mV V(IN), V(OUT), falling 8
Forward threshold, rising V(FWDTH) 85 96 110 mV V(IN), V(OUT), rising 8
FLT pull-down resistance R(FLT) 40 85 160 Ω V(OVP) = 2 V, I(FLT) = 5 mA sinking 8
FLT input leakage current I(FLT) -200 200 nA 0 V ≤ V(FLT) ≤ 42 V 8
TSD threshold, rising T(TSD) 157 ºC 8
TSD hysteresis T(TSDhyst) 10 ºC 8
UVLO turnon delay UVLO_tON(dly) 250 µs UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dvdt) = open 9
UVLO turnoff delay UVLO_toff(dly) 10 µs UVLO↓ (100 mV below V(UVLOF)) to FLT↓ 9
SHUTDOWN exit delay tSD(dly) 250 µs SHDN↑ to V(OUT) = 100 mV, C(dvdt) = open 9
SHUTDOWN entry delay tSD(dly) 10 µs SHDN↓ (below V(SHUTF)) to FLT↓ 9
OVP exit delay tOVP(dly) 200 µs OVP↓ (20 mV below V(OVPF)) to V(OUT) = 100 mV 9
OVP disable delay tOVP(dly) 6 µs OVP↑ (20 mV above V(OVPR)) to FLT↓ 9
Fast-trip comparator delay tFASTTRIP(dly) 250 ns I(OUT) > I(FASTRIP) 9
Retry delay in TSD tretry 512 ms 9
Output ramp time tdVdT 1.6 ms SHDN↑ to V(OUT) = 23.9 V, with C(dVdT) = open 9
Input voltage (absolute max) IN, IN-OUT IN -45 45 V 5
Input voltage 10 ms transient IN -55 55 V IN, IN-OUT (10 ms transient), TA = 25°C 5
IN, OUT, FLT, UVLO, SHDN to RTN -0.3 45 V 5
OVP, dVdT, ILIM, IMON, MODE to RTN -0.3 5 V 5
RTN voltage RTN -45 0.3 V 5
Sink current IFLT, IdVdT, ISHDN 10 mA 5
Operating junction temperature (abs max) TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Input voltage IN (recommended) IN -42 42 V 5
ILIM resistance ILIM 5.36 120 kΩ 5
Operating junction temperature TJ -40 25 125 °C 5
Junction-to-ambient thermal resistance RθJA 30.2 °C/W RHF (VQFN) 24 pins 6

CAD (KiCad official)

  • Symbol: TPS26400RHFR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: VQFN-24(4x5) (KiCad packages3D, STEP)
  • 3D model files: tps26400rhfr-etched.step / tps26400rhfr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps26400rhfr.step / tps26400rhfr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (56 pp, sha256 6532dc40aab68268, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF