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TPS259830ONRGER

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TEXAS INSTRUMENTS Global Sourcing Parts, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS259830ONRGER

TEXAS INSTRUMENTS · Global Sourcing Parts · VQFN-24-EP(4x4)

TPS259830ONRGER from TEXAS INSTRUMENTS, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input to the eFuse, rated for a 2.7 V to 26 V operating range with a 30 V absolute maximum.
2 IN power_in Power input to the eFuse, rated for a 2.7 V to 26 V operating range with a 30 V absolute maximum.
3 IN power_in Power input to the eFuse, rated for a 2.7 V to 26 V operating range with a 30 V absolute maximum.
4 GND power_in Ground; connect to the system ground plane.
5 GND power_in Ground; connect to the system ground plane.
6 EN/UVLO input Active-high enable; a resistor divider from input supply to GND sets the undervoltage lockout threshold, and the pin must not be left floating.
7 ITIMER output A capacitor from this pin to GND sets the overcurrent blanking interval; leaving it open gives the fastest overcurrent response, and shorting it to GND is detected as a fault that shuts the part down.
8 ILIM output An external resistor from this pin to GND sets the output current limit and fast-trip thresholds, and the pin must not be left floating.
9 IMON output Analog load-current monitor that sources a current proportional to load current, convertible to a voltage by a resistor to GND.
10 RETRY_DLY output A capacitor from this pin to GND sets the time after a fault shutdown before automatic restart; connecting it to GND selects latch-off operation with no auto-retries.
11 NRETRY output A capacitor from this pin to GND sets the number of automatic restart attempts after a fault; connecting it to GND allows indefinite retries.
12 OVLO input A resistor divider from input supply to GND sets the overvoltage lockout threshold, and the pin must not be left floating.
13 PG output Active-high power-good open-drain output that requires an external pullup to an external supply and remains low when VIN is below VUVP.
14 GND power_in Ground; connect to the system ground plane.
15 dVdt/BGATE output A capacitor from this pin to GND sets the output turn-on slew rate (leave floating for the fastest start-up slew), and the pin can also drive an external FET for reverse current blocking in the off/disabled state.
16 IN power_in Power input to the eFuse, rated for a 2.7 V to 26 V operating range with a 30 V absolute maximum.
17 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
18 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
19 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
20 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
21 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
22 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
23 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
24 OUT power_out Protected power output from the internal FET; absolute maximum VOUT is -0.8 V to min(30 V, VIN + 0.3 V).
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer TEXAS INSTRUMENTS
Package VQFN-24-EP(4x4)
Category Global Sourcing Parts
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 2.7 26 V 6
Enable pin voltage range VEN/UVLO 6 V 6
OVLO pin voltage range VOVLO 6 V 6
PG pin voltage range VPG 6 V 6
ITIMER pin capacitor voltage rating VITIMER 4 V 6
NRETRY pin capacitor voltage rating VNRETRY 4 V 6
RETRY_DLY pin capacitor voltage rating VRETRY_DLY 4 V 6
ILIM pin resistor value range RILIM 82 1650 Ω 6
Continuous switch current IN to OUT IMAX 18 A 6
Junction temperature range TJ -40 125 °C 6
Maximum input voltage range VIN -0.3 30 V 5
Maximum output voltage range VOUT -0.8 V 5
Maximum enable pin voltage range VEN/UVLO -0.3 7 V 5
Maximum OVLO pin voltage range VOVLO 7 V 5
Maximum PG pin voltage range VPG -0.3 7 V 5
Maximum soldering temperature TLEAD 300 °C 5
Maximum storage temperature Tstg -65 150 °C 5
Electrostatic discharge, human body model V(ESD) -2000 2000 V HBM, per ANSI/ESDA/JEDEC JS-001 5
Electrostatic discharge, charged device model V(ESD) -1000 1000 V CDM, per ANSI/ESDA/JEDEC JS-002 5
Current monitor gain (IIMON:IOUT) GIMON 235.29 243 249.63 µA/A 3 A ≤ IOUT ≤ min(18 A, ILIM) 7
IOUT current limit threshold ILIM 1.526 2.03 2.48 A RILIM = 773 Ω 7
IOUT current limit threshold ILIM 4.36 4.98 5.66 A RILIM = 300 Ω 7
IOUT current limit threshold ILIM 7.1 8.13 8.96 A RILIM = 182 Ω 7
IOUT current limit threshold ILIM 12.6 14.729 16.23 A RILIM = 100 Ω 7
IOUT current limit threshold ILIM 16.3 17.526 18.8 A RILIM = 84 Ω 7
IN quiescent current IQ(ON) 800 1000 µA VEN ≥ VUVLO(R) 7
IN OFF current IQ(OFF) 204 300 µA VSD(F) < VEN < VUVLO 7
IN shutdown current ISD 3.7 15 µA VEN < VSD(F) 7
EN/UVLO pin voltage threshold to turn ON FET (rising) VUVLO(R) 1.18 1.2 1.23 V VEN rising 7
EN/UVLO pin voltage threshold to turn OFF FET (falling) VUVLO(F) 1.08 1.1 1.13 V VEN falling 7
EN/UVLO pin voltage threshold for lowest shutdown current VSD(F) 0.59 0.8 V VEN falling 7
OVLO pin voltage threshold (rising) VOV(R) 1.1 1.21 1.25 V VOVLO rising 7
OVLO pin voltage threshold (falling) VOV(F) 1.08 1.1 1.125 µA VOVLO falling 7
PG pin low voltage (PG de-asserted) VPGD 651 786 mV VIN < VUVP(F), VEN < VSD(F), IPG = 26 µA 7
RON when PG is asserted RON(PGA) 4.2 6.4 mΩ 7
IN-OUT ON resistance RON 2.7 3.2 mΩ TJ = 25℃, IOUT = 2 A 7
IN-OUT ON resistance RON 4.5 mΩ TJ = -40 to 125℃, IOUT = 2 A 7
VIN - VOUT threshold when PG is de-asserted VPGTHD 0.217 0.326 0.451 V 8
RETRY_DLY oscillator comparator threshold (rising) VRETRY_DLY(R) 0.95 1.1 1.19 V 8
RETRY_DLY oscillator comparator threshold (falling) VRETRY_DLY(F) 0.25 0.35 0.43 V 8
RETRY_DLY pin bias current IRETRY_DLY 1.7 2.05 3.25 µA 8
NRETRY oscillator comparator threshold (rising) VNRETRY(R) 0.95 1.1 1.19 V 8
NRETRY oscillator comparator threshold (falling) VNRETRY(F) 0.24 0.35 0.445 V 8
NRETRY pin bias current INRETRY 1.7 2.05 3.25 µA 8
ITIMER pin discharge current IITIMER 1.48 2.1 2.65 µA IFT > IOUT > ILIM 8
ITIMER internal pull-up resistance RITIMER 15 23 33 kΩ IOUT < ILIM 8
ITIMER pin internal pull-up voltage VINT 2.3 2.5 2.7 V IOUT < ILIM 8
ITIMER discharge differential voltage threshold ΔVITIMER 0.8 0.98 1.15 V IFT > IOUT > ILIM, ITIMER voltage falling 8
dVdT/BGATE pin charging current during inrush IdVdt 3.6 4.76 6 µA 8
Thermal shutdown threshold TSD 150 °C TJ Rising 8
Junction-to-ambient thermal resistance RθJA 34.6 °C/W JEDEC 4-layer PCB (2s2p) simulation 6
Junction-to-case (top) thermal resistance RθJC(top) 36.7 °C/W JEDEC 4-layer PCB (2s2p) simulation 6
Junction-to-board thermal resistance RθJB 11.2 °C/W JEDEC 4-layer PCB (2s2p) simulation 6
Junction-to-top characterization parameter ΨJT 3 °C/W JEDEC 4-layer PCB (2s2p) simulation 6
Junction-to-board characterization parameter ΨJB 11.2 °C/W JEDEC 4-layer PCB (2s2p) simulation 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.6 °C/W JEDEC 4-layer PCB (2s2p) simulation 6
IOUT circuit-breaker threshold during ILIM pin short to GND ICB 15 A RILIM = Short to GND, TJ = 25℃ 7
VOUT voltage threshold for current limit foldback VFB 0.91 V 7
Short-circuit fast trip threshold (Steady-state) IFT 86.4 A Steady-state, PG asserted 7
IN undervoltage protection threshold (rising) VUVP 2.53 V VIN rising 7

CAD (KiCad official)

  • Symbol: TPS259830ONRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps259830onrger-etched.step / tps259830onrger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps259830onrger.step / tps259830onrger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TEXAS INSTRUMENTS datasheet (56 pp, sha256 79d2183e0c129942, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF