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Contents

README

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TPS259827ONRGET

Texas Instruments · Surge Protection Devices (SPDs) · VQFN-24(4x4)

TPS259827ONRGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power supply input voltage range 2.7V to 24V; exposed thermal pad must be evenly soldered to input power plane for proper heat dissipation and optimal current distribution.
2 IN power_in Power supply input voltage range 2.7V to 24V; exposed thermal pad must be evenly soldered to input power plane for proper heat dissipation and optimal current distribution.
3 IN power_in Power supply input voltage range 2.7V to 24V; exposed thermal pad must be evenly soldered to input power plane for proper heat dissipation and optimal current distribution.
4 GND power_in Ground connection to system ground plane.
5 GND power_in Ground connection to system ground plane.
6 EN/UVLO input High-level active enable pin; resistor voltage divider from input power to GND adjusts UVLO threshold per VINUVLO = VUVLO(R) × (RVL1 + RVL2) / RVL2, do not leave floating.
7 ITIMER output Capacitor to GND sets overcurrent blanking interval during which output current may temporarily exceed ILIM but remain below 2.1×ILIM threshold before circuit breaker activation; leave open for fastest response.
8 ILIM output External resistor to GND sets output current limit threshold ILIM and fast-trip threshold per RILIM = 1460/(ILIM - 0.11) with range 82Ω to 1650Ω; do not leave floating.
9 IMON output Analog load current monitor providing output current proportional to load current with gain 246 µA/A typical at ±1.5% accuracy; resistor to GND converts to voltage signal for ADC.
10 RETRY_DLY output Capacitor to GND sets delay time from fault shutdown to automatic restart per tRETRY_DLY = 128 × CRETRY_DLY / IRETRY_DLY; connect to GND for latch mode without auto-retry.
11 NRETRY output Capacitor to GND sets number of automatic restart attempts after fault with discrete levels at 4, 16, 64, 256, 1024 retries; connect to GND for infinite retry attempts.
12 LDSTRT input Load detection/handshake signal; capacitor to GND sets time window requiring load to pull pin low after PG valid per tLDSTRT = CLDSTRT × VLDSTRT / ILDSTRT; connect to GND if feature not used, do not leave floating.
13 PG tri_state High-level active power good indicator, open-drain output requiring external pull-up resistor to external power; valid when FET fully enhanced and output reaches full voltage, stays low when VIN < VUVP.
14 GND power_in Ground connection to system ground plane.
15 dVdt output Capacitor to GND sets output turn-on slew rate limiting inrush current per CdVdt = 4600/SR with bias voltage internal; leave floating for fastest slew rate and minimum startup time.
16 IN power_in Power supply input voltage range 2.7V to 24V; part of multi-pin input connection.
17 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
18 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
19 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
20 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
21 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
22 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
23 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
24 OUT power_out Power supply output, maximum continuous current 15A; integrated MOSFET switch with 2.7mΩ typical on-resistance at 25°C.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Circuit Protection
Pins 25

CAD (KiCad official)

  • Symbol: TPS259827ONRGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps259827onrget-etched.step / tps259827onrget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps259827onrget.step / tps259827onrget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 f4a0f06cfbd81f26, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF