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TPS259824ONRGET

Texas Instruments · Supervisor And Reset ICs · VQFN-24-EP(4x4)

TPS259824ONRGET from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input for connection to input power supply plane for current distribution and heat dissipation.
2 IN power_in Power input for connection to input power supply plane for current distribution and heat dissipation.
3 IN power_in Power input for connection to input power supply plane for current distribution and heat dissipation.
4 GND power_in System ground reference.
5 GND power_in System ground reference.
6 EN/UVLO input High-level active enable pin with external resistor divider to ground for adjustable UVLO threshold; must not float.
7 ITIMER output Overcurrent blanking timer pin; capacitor to ground sets delay before overcurrent protection response.
8 ILIM output Current limit threshold pin; external resistor to ground sets maximum output current limit and fast-trip threshold.
9 IMON output Analog load current monitor output providing current proportional to FET load current.
10 RETRY_DLY output Auto-retry delay timer pin; capacitor to ground sets time interval between fault shutdown and restart attempts.
11 NRETRY output Auto-retry counter pin; capacitor to ground sets maximum number of restart attempts after fault.
12 LDSTRT input Load detection/handshake input pin; capacitor to ground sets timeout window for pull-low signal after PG assertion.
13 PG output Open-drain power-good output, active high when FET fully conducts and output reaches maximum voltage.
14 GND power_in System ground reference.
15 dVdt output Output slew rate control pin; capacitor to ground adjusts turn-on ramp rate; leave floating for fastest slew.
16 IN power_in Power input for connection to input power supply plane for current distribution and heat dissipation.
17 OUT power_out Power output connection to load.
18 OUT power_out Power output connection to load.
19 OUT power_out Power output connection to load.
20 OUT power_out Power output connection to load.
21 OUT power_out Power output connection to load.
22 OUT power_out Power output connection to load.
23 OUT power_out Power output connection to load.
24 OUT power_out Power output connection to load.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: TPS259824ONRGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps259824onrget-etched.step / tps259824onrget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps259824onrget.step / tps259824onrget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 f4a0f06cfbd81f26, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF