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TPS259823LNRGET

Texas Instruments · Surge Protection Devices (SPDs) · VQFN-24(4x4)

TPS259823LNRGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power supply input, one of multiple power input pins including thermal pad for heat dissipation and current distribution.
2 IN power_in Power supply input, one of multiple power input pins including thermal pad for heat dissipation and current distribution.
3 IN power_in Power supply input, one of multiple power input pins including thermal pad for heat dissipation and current distribution.
4 GND power_in Ground connection to system ground reference plane.
5 GND power_in Ground connection to system ground reference plane.
6 EN/UVLO input High-level active enable pin with external resistor divider from IN to GND for setting under-voltage lockout threshold; must not be left floating, recommended voltage 6V maximum.
7 ITIMER output Analog output pin with external capacitor to GND setting overcurrent blanking interval; allows temporary overcurrent up to 2.1× ILIM before circuit protection activates.
8 ILIM output Analog output pin with external resistor to GND (82Ω to 1650Ω) setting output current limit threshold from 2A to 15A and fast trip threshold at 2.1× ILIM; must not be left floating.
9 IMON output Analog load current monitor output with gain of 246 µA/A; provides current proportional to output load current, convertible to voltage by external resistor to GND.
10 RETRY_DLY output Analog output pin with external capacitor to GND setting time delay from fault shutdown to automatic restart attempt; connect to GND for latching mode without auto-retry.
11 NRETRY output Analog output pin with external capacitor to GND setting number of automatic restart attempts after fault; connect to GND for infinite retry operation.
12 LDSTRT input Load detection/handshake signal input with external capacitor to GND setting time window for external circuit to pull this pin low after PG assertion; must not be left floating.
13 PG output High-level active power good open-drain digital output asserted when FET is fully on and output voltage reaches maximum; requires external pull-up resistor, remains low when VIN < VUVP.
14 GND power_in Ground connection to system ground reference plane.
15 dVdt output Analog output pin with external capacitor to GND for setting output voltage slew rate during startup to manage inrush current; leave floating for maximum slew rate.
16 IN power_in Power supply input, one of multiple power input pins including thermal pad for heat dissipation and current distribution.
17 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
18 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
19 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
20 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
21 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
22 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
23 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
24 OUT power_out Power supply output from integrated electronic fuse, one of multiple output pins rated for 15A maximum continuous current.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Circuit Protection
Pins 25

CAD (KiCad official)

  • Symbol: TPS259823LNRGET
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps259823lnrget-etched.step / tps259823lnrget-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps259823lnrget.step / tps259823lnrget.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 f4a0f06cfbd81f26, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF