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TPS259823LNRGER

Public Made by Adom

by adom

Texas Instruments Supervisor And Reset ICs, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps259823lnrgerfactory-2.0.0extractor-text

Verified TPS259823LNRGER

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS259823LNRGER · VQFN-24(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 58-page datasheet
  • ✓distributor: lcsc C2155779, digikey 296-53586-2-ND, mouser 595-TPS259823LNRGER
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-9f88i7dt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps259823lnrger.kicad_sym✓ tps259823lnrger.kicad_mod✓ tps259823lnrger.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 4h ago
viewers tps259823lnrger: viewers · Ray 4h ago
package.json Publish 0.1.0 · Ray 4h ago
page.json Set visibility: public · Ray 4h ago
README.md Publish 0.1.0 · Ray 4h ago
tps259823lnrger-etched.glb Publish 0.1.0 · Ray 4h ago
tps259823lnrger-etched.step tps259823lnrger: factory component page (tier=mfr) · Ray 4h ago
tps259823lnrger-hero.glb tps259823lnrger: hero GLB from the etched model (keeps the MPN mark) · Ray 4h ago
tps259823lnrger-hero.overlay.json Publish 0.1.0 · Ray 4h ago
tps259823lnrger.glb Publish 0.1.0 · Ray 4h ago
tps259823lnrger.kicad_mod Publish 0.1.0 · Ray 4h ago
tps259823lnrger.kicad_sym Publish 0.1.0 · Ray 4h ago
tps259823lnrger.lbr Publish 0.1.0 · Ray 4h ago
tps259823lnrger.step Publish 0.1.0 · Ray 4h ago
verification.json Verified: Published by the parts factory: tier mfr, 25 pins · Ray 4h ago

TPS259823LNRGER

Texas Instruments · Supervisor And Reset ICs · VQFN-24(4x4)

TPS259823LNRGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input; recommended input voltage range is 2.7V to 24V with 30V absolute maximum, and the exposed pad must be soldered to the input power plane uniformly for heat dissipation.
2 IN power_in Power input; recommended input voltage range is 2.7V to 24V with 30V absolute maximum.
3 IN power_in Power input; recommended input voltage range is 2.7V to 24V with 30V absolute maximum.
4 GND power_in Connect to system ground.
5 GND power_in Connect to system ground.
6 EN/UVLO input Active high enable for the device; a resistor divider from input supply to GND adjusts the undervoltage lockout threshold, and the pin must not be left floating.
7 ITIMER output A capacitor from this pin to GND sets the overcurrent blanking interval; leave open for fastest overcurrent response and short to GND is detected as a fault that shuts the part down.
8 ILIM output An external resistor from this pin to GND sets the output current limit and fast-trip thresholds, and the pin must not be left floating.
9 IMON output Analog output load current monitor that sources a current proportional to load current, convertible to a voltage with a resistor to GND.
10 RETRY_DLY output A capacitor from this pin to GND sets the delay after a fault shutdown before automatic restart; connect to GND for latch-off operation.
11 NRETRY output A capacitor from this pin to GND sets the number of automatic restart attempts after a fault; connect to GND for indefinite retry.
12 LDSTRT input Load detect/handshake input; a capacitor to GND sets the time after PG assertion within which this pin must be pulled low, and it must be connected to GND if the feature is unused and must not be left floating.
13 PG output Active high power good open-drain output that requires an external pull-up and remains logic low when VIN is below VUVP.
14 GND power_in Connect to system ground.
15 dVdt output A capacitor from this pin to GND sets the output turn-on slew rate; leave floating for the fastest start-up slew rate.
16 IN power_in Power input; recommended input voltage range is 2.7V to 24V with 30V absolute maximum.
17 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
18 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
19 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
20 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
21 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
22 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
23 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
24 OUT power_out Power output that delivers the switched and current-limited load current from the internal FET.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Power Management (PMIC)
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN Maximum Input Voltage Range VIN -0.3 30 V 7
VOUT Maximum Output Voltage Range VOUT -0.8 V max is min(30V, VIN + 0.3) as printed 7
VEN/UVLO Maximum Enable Pin Voltage Range VEN/UVLO -0.3 7 V 7
VLDSTRT Maximum LDSTRT Pin Voltage Range VLDSTRT 7 V 7
VPG Maximum PG Pin Voltage Range VPG -0.3 7 V 7
TLEAD Maximum Soldering Temperature TLEAD 300 °C 7
Tstg Storage temperature Tstg -65 150 °C 7
VIN Input Voltage Range VIN 2.7 24 V 7
VEN/UVLO Enable Pin Voltage Range VEN/UVLO 6 V 7
VLDSTRT LDSTRT Pin Capacitor Voltage Rating VLDSTRT 4 V 7
VPG PG Pin Voltage Range VPG 6 V 7
VITIMER ITIMER Pin Capacitor Voltage Rating VITIMER 4 V 7
VNRETRY NRETRY Pin Capacitor Voltage Rating VNRETRY 4 V 7
VRETRY_DLY RETRY_DLY Pin Capacitor Voltage Rating VRETRY_DLY 4 V 7
RILIM ILIM Pin Resistor RILIM 82 1650 Ω 7
IMAX Continuous Switch Current IN to OUT IMAX 15 A 7
TJ Junction temperature TJ -15 125 °C 8
VIN Input Voltage Range VIN 2.7 24 V 8
IQ IN Quiescent Current IQ 800 1200 µA VEN ≥ VUVLO(R) 8
ISD IN Shutdown Current ISD 204 300 µA VSD < VEN < VUVLO 8
ISD IN Shutdown Current ISD 3.67 20 µA VEN < VSD 8
IN Undervoltage Protection Threshold (rising) VUVP 2.46 2.53 2.6 V VIN Rising 8
IN Undervoltage Protection Threshold (falling) VUVP 2.35 2.42 2.49 V VIN Falling 8
Overvoltage Protection Threshold (rising) VOVP(R) 7.39 7.6 7.76 V TPS259823x, VIN Rising 8
Overvoltage Protection Threshold (falling) VOVP(F) 7.22 7.4 7.55 V TPS259823x, VIN Falling 8
Current Monitor Gain (IIMON:IOUT) GIMON 238.6 246 253.4 µA/A 3A ≤ IOUT ≤ min(15A, ILIM), -40°C ≤ TA ≤ 75°C 8
IOUT Current Limit Threshold ILIM 1.76 2 2.17 A RILIM = 773Ω, TJ = 25°C 9
IOUT Current Limit Threshold ILIM 1.53 2 2.43 A RILIM = 773Ω, TJ = -40 to 125°C 9
IOUT Current Limit Threshold ILIM 4.75 4.98 5.23 A RILIM = 300Ω, TJ = 25°C 9
IOUT Current Limit Threshold ILIM 4.36 4.98 5.66 A RILIM = 300Ω, TJ = -40 to 125°C 9
IOUT Current Limit Threshold ILIM 7.77 8.13 8.54 A RILIM = 182Ω, TJ = 25°C 9
IOUT Current Limit Threshold ILIM 7.23 8.13 9.07 A RILIM = 182Ω, TJ = -40 to 125°C 9
IOUT Current Limit Threshold ILIM 13.56 14.71 15.66 A RILIM = 100Ω, TJ = 25°C 9
IOUT Current Limit Threshold ILIM 12.85 14.71 15.99 A RILIM = 100Ω, TJ = -40 to 125°C 9
ON State Resistance RON 2.7 3.2 mΩ TJ = 25°C, IOUT = 2A 9
ON State Resistance RON 4.5 mΩ TJ = -40 to 125°C, IOUT = 2A 9
EN/UVLO Pin Voltage Threshold (rising) VUVLO(R) 1.18 1.2 1.23 V VEN Rising 9
EN/UVLO Pin Voltage Threshold (falling) VUVLO(F) 1.08 1.1 1.13 V VEN Falling 9
EN/UVLO Pin Voltage Threshold for Lowest Shutdown Current VSD 0.59 0.8 V VEN Falling 9
PG Pin Low Voltage (PG de-asserted) VPGD 651 786 mV VIN < VUVP, VEN < VSD, IPG = 26µA 9
PG Pin Low Voltage (PG de-asserted) VPGD 320 mV VIN = 3.3V, IPG ≤ 5mA 9
PG Pin Low Voltage (PG de-asserted) VPGD 100 mV VIN ≥ 5V, IPG ≤ 5mA 9
VIN - VOUT Threshold when PG is de-asserted VPGTHD 0.224 0.326 0.45 V 9
RETRY_DLY Oscillator Hysteresis VRETRY_DLY_HYS 0.65 0.75 0.85 V 9
NRETRY Oscillator Hysteresis VNRETRY_HYS 0.65 0.75 0.85 V 9
RETRY_DLY Pin Bias Current IRETRY_DLY 1.7 2.05 2.5 µA 9
NRETRY Pin Bias Current INRETRY 1.7 2.05 2.5 µA 9
ITIMER Discharge Current IITIMER 1.4 2.1 2.8 µA ISC > IOUT > ILIM 9
ITIMER Comparator Voltage Threshold Delta ΔVITIMER 0.7 0.98 1.3 V ISC > IOUT > ILIM, ITIMER Voltage Falling 10
LDSTRT Rising Threshold VLDSTRT 1.1 1.21 1.3 V LDSTRT voltage rising 10
LDSTRT Charging Current ILDSTRT 1.7 2.05 2.4 µA PG asserted 10
dVdt Pin Charging Current IdVdt 2 4.6 6.33 µA 10
Junction-to-ambient thermal resistance RθJA 34.6 °C/W JEDEC 4-layer PCB (2s2p), 2oz Cu, 3x2 via array 8
Junction-to-case (top) thermal resistance RθJC(top) 36.7 °C/W JEDEC 4-layer PCB (2s2p), 2oz Cu, 3x2 via array 8
Junction-to-board thermal resistance RθJB 11.2 °C/W JEDEC 4-layer PCB (2s2p), 2oz Cu, 3x2 via array 8
Junction-to-top characterization parameter ΨJT 3 °C/W JEDEC 4-layer PCB (2s2p), 2oz Cu, 3x2 via array 8
Junction-to-board characterization parameter ΨJB 11.2 °C/W JEDEC 4-layer PCB (2s2p), 2oz Cu, 3x2 via array 8
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.6 °C/W JEDEC 4-layer PCB (2s2p), 2oz Cu, 3x2 via array 8

CAD (KiCad official)

  • Symbol: TPS259823LNRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps259823lnrger-etched.step / tps259823lnrger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps259823lnrger.step / tps259823lnrger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (58 pp, sha256 655c21dbf6b91a3c, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF