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TPS259803ONRGER

Texas Instruments · Surge Protection Devices (SPDs) · VQFN-24-EP(4x4)

TPS259803ONRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Power input for the eFuse, with a recommended range of 2.7 V to 24 V and an absolute maximum of 30 V.
2 IN power_in Power input for the eFuse, with a recommended range of 2.7 V to 24 V and an absolute maximum of 30 V.
3 IN power_in Power input for the eFuse, with a recommended range of 2.7 V to 24 V and an absolute maximum of 30 V.
4 GND power_in Connect to system ground.
5 GND power_in Connect to system ground.
6 EN/UVLO input Active-high enable input whose resistor divider from IN sets the UVLO threshold; it must not be left floating and the recommended voltage is 6 V maximum (absolute maximum 7 V).
7 ITIMER output A capacitor to GND sets the overcurrent blanking interval, which should be left open for the fastest response, and shorting it to GND causes a device fault shutdown.
8 ILIM output A resistor to GND sets the output current limit and fast-trip threshold, with RILIM recommended between 182 Ω and 1650 Ω, and it must not be left floating.
9 IMON output Analog load-current monitor output proportional to load current with a gain of 246 µA/A typical, converted to voltage by a resistor to GND and limited to 1 V at VIN = 2.7 V, 1.8 V at 3.3 V, and 3.3 V above 5 V.
10 RETRY_DLY output A capacitor to GND sets the delay before an automatic restart after a fault, and connecting it to GND selects latch-off with no auto-retry; the capacitor voltage rating is 4 V.
11 NRETRY output A capacitor to GND sets the number of automatic restarts after a fault, and connecting it to GND selects infinite retries; the capacitor voltage rating is 4 V.
12 LDSTRT input Load-detect/handshake input where a capacitor to GND sets the time window after PG asserts in which the pin must be pulled low, it must not be left floating, and it should be tied to GND if unused; the capacitor rating is 4 V.
13 PG output Active-high power-good open-drain output that requires an external pull-up and asserts when the FET is fully enhanced and the output reaches its maximum voltage, held low when VIN < VUVP, with a recommended voltage of 6 V maximum.
14 GND power_in Connect to system ground.
15 dVdt output A capacitor to GND sets the output turn-on slew rate, with the pin left open for the fastest slew rate during start-up, and the recommended capacitor voltage rating is VIN + 4 V.
16 IN power_in Power input for the eFuse, with a recommended range of 2.7 V to 24 V and an absolute maximum of 30 V.
17 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
18 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
19 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
20 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
21 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
22 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
23 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
24 OUT power_out Switched power output from the internal FET, with an absolute maximum voltage between -0.8 V and the lesser of 30 V and VIN + 0.3 V.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Circuit Protection
Pins 25

CAD (KiCad official)

  • Symbol: TPS259803ONRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps259803onrger-etched.step / tps259803onrger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps259803onrger.step / tps259803onrger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 62f43bf320ab43a8, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF