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TPS25940ARVCT

Texas Instruments · Surge Suppressors · WQFN-20(4x3)

TPS25940ARVCT from Texas Instruments, in a WQFN-20(4x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DEVSLP input Active-high DevSleep mode control that activates the low-power DevSleep mode; recommended input range is 0 to 18 V.
2 PGOOD output Active-high power-good output that goes high when PGTH crosses its threshold; open-drain, sink current limited to 10 mA, recommended range 0 to 18 V.
3 PGTH input Positive input of the PGOOD comparator; recommended input range is 0 to 18 V.
4 OUT power_out Power output of the device; recommended range 0 to 18 V, with 0.1 µF external capacitance listed for OUT.
5 OUT power_out Power output of the device; recommended range 0 to 18 V, with 0.1 µF external capacitance listed for OUT.
6 OUT power_out Power output of the device; recommended range 0 to 18 V, with 0.1 µF external capacitance listed for OUT.
7 OUT power_out Power output of the device; recommended range 0 to 18 V, with 0.1 µF external capacitance listed for OUT.
8 OUT power_out Power output of the device; recommended range 0 to 18 V, with 0.1 µF external capacitance listed for OUT.
9 IN power_in Power input and supply voltage of the device; recommended range 2.7 to 18 V, absolute maximum 20 V (22 V for 10 ms transients).
10 IN power_in Power input and supply voltage of the device; recommended range 2.7 to 18 V, absolute maximum 20 V (22 V for 10 ms transients).
11 IN power_in Power input and supply voltage of the device; recommended range 2.7 to 18 V, absolute maximum 20 V (22 V for 10 ms transients).
12 IN power_in Power input and supply voltage of the device; recommended range 2.7 to 18 V, absolute maximum 20 V (22 V for 10 ms transients).
13 IN power_in Power input and supply voltage of the device; recommended range 2.7 to 18 V, absolute maximum 20 V (22 V for 10 ms transients).
14 EN/UVLO input Sets the programmable undervoltage lockout threshold; an undervoltage event opens the internal FET and asserts FLT, and pulling it to GND resets the fault latch in TPS25940L; recommended range 0 to 18 V.
15 OVP input Sets the programmable overvoltage protection threshold; an overvoltage event opens the internal FET and asserts FLT; recommended range 0 to 18 V.
16 GND power_in Ground; must be connected to the exposed PowerPAD, which must be tied to a PCB ground plane using multiple vias.
17 ILIM bidirectional A resistor from this pin to GND sets the overload and short-circuit current limit; recommended resistance 16.9 kΩ to 150 kΩ and voltage 0 to 3 V.
18 dVdT bidirectional A capacitor from this pin to GND sets the output voltage ramp rate; recommended capacitance up to 470 nF, voltage 0 to 3 V, sink current limited to 10 mA.
19 IMON output Sources a scaled-down ratio of the internal FET current, which a resistor to GND converts to a proportional analog voltage; recommended range 0 to 6 V, absolute maximum 7 V.
20 FLT output Open-drain fault indicator that goes low for undervoltage, overvoltage, reverse voltage, or thermal shutdown events; recommended range 0 to 18 V, sink current limited to 10 mA.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-20(4x3)
Category TVS/Fuse/Board Level Protection
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range (IN, OUT, PGTH, PGOOD, EN/UVLO, OVP, DEVSLP, FLT) -0.3 20 V 4
IN input voltage, 10 ms transient 22 V 10 ms transient 4
Input voltage range (dVdT, ILIM) -0.3 3.6 V 4
Input voltage range (IMON) -0.3 7 V 4
Sink current (PGOOD, FLT, dVdT) 10 mA PGOOD, FLT, dVdT 4
Maximum junction temperature TJ TJ -40 150 °C 4
Input voltage range IN 2.7 18 V 4
Input voltage range (EN/UVLO, OVP, DEVSLP, OUT, PGTH, PGOOD, FLT) 0 18 V 4
Input voltage range (dVdT, ILIM) 0 3 V 4
Input voltage range (IMON) 0 6 V 4
Resistance ILIM 16.9 150 kΩ 4
External capacitance OUT 0.1 µF 4
External capacitance dVdT 470 nF 4
Operating junction temperature range TJ TJ -40 25 125 °C 4
Input voltage range V(IN) operating V(IN) 2.7 18 V 6
Internal UVLO threshold, rising V(UVR) 2.2 2.3 2.4 V 6
Supply current, enabled IQ(ON) 140 210 300 µA V(EN/UVLO) = 2 V, V(IN) = 3 V 6
Supply current, enabled IQ(ON) 140 199 260 µA V(EN/UVLO) = 2 V, V(IN) = 12 V 6
Supply current, enabled IQ(ON) 140 202 270 µA V(EN/UVLO) = 2 V, V(IN) = 18 V 6
Supply current, disabled IQ(OFF) 4 8.6 15 µA V(EN/UVLO) = 0 V, V(IN) = 3 V 6
Supply current, disabled IQ(OFF) 6 15 20 µA V(EN/UVLO) = 0 V, V(IN) = 12 V 6
Supply current, disabled IQ(OFF) 8 18.5 25 µA V(EN/UVLO) = 0 V, V(IN) = 18 V 6
Supply current, DevSleep mode IQ(DEVSLP) 70 95 130 µA V(DEVSLP) = 0 V, V(IN) = 2.7V to 18V 6
EN/UVLO threshold voltage, rising V(ENR) 0.97 0.99 1.01 V 6
EN/UVLO threshold voltage, falling V(ENF) 0.9 0.92 0.94 V 6
Overvoltage threshold voltage, rising V(OVPR) 0.97 0.99 1.01 V 6
Overvoltage threshold voltage, falling V(OVPF) 0.9 0.92 0.94 V 6
DEVSLP threshold voltage, rising V(DEVSLPR) 1.6 1.85 2 V 6
DEVSLP threshold voltage, falling V(DEVSLPF) 0.8 0.96 1.1 V 6
dVdT charging current I(dVdT) 0.85 1 1.15 µA V(dVdT) = 0 V 6
dVdT discharging resistance R(dVdT) 16 24 Ω EN/UVLO = 0 V, I(dVdT) = 10 mA sinking 6
dVdT maximum capacitor voltage V(dVdTmax) 2.6 2.88 3.1 V 6
dVdT to OUT gain GAIN(dVdT) 11.65 11.9 12.05 V/V 6
Current limit I(LIM) I(LIM) 0.53 0.58 0.63 A R(ILIM) = 150 kΩ, (V(IN) - V(OUT)) = 1 V 6
Current limit I(LIM) I(LIM) 0.9 0.99 1.07 A R(ILIM) = 88.7 kΩ, (V(IN) - V(OUT)) = 1 V 6
Current limit I(LIM) I(LIM) 1.92 2.08 2.25 A R(ILIM) = 42.2 kΩ, (V(IN) - V(OUT)) = 1 V 6
Current limit I(LIM) I(LIM) 3.25 3.53 3.81 A R(ILIM) = 24.9 kΩ, (V(IN) - V(OUT)) = 1 V 6
Current limit I(LIM) I(LIM) 4.78 5.2 5.62 A R(ILIM) = 16.9 kΩ, (V(IN) - V(OUT)) = 1 V 6
DevSleep mode current limit I(DEVSLP(LIM)) 0.55 0.67 0.8 A 6
Short-circuit current limit IOS IOS 1.91 2.07 2.24 A R(ILIM) = 42.2 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT)) = 5 V 7
Short-circuit current limit IOS IOS 3.21 3.49 3.77 A R(ILIM) = 24.9 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT)) = 5 V 7
Short-circuit current limit IOS IOS 4.7 5.11 5.52 A R(ILIM) = 16.9 kΩ, V(VIN) = 12 V, (V(IN) -V(OUT)) = 5 V, -40°C ≤ TJ ≤ 85°C 7
Gain factor I(IMON):I(OUT) GAIN(IMON) 47.78 52.3 57.23 µA/A 1 A ≤ I(OUT) ≤ 5 A 7
IN to OUT ON resistance RON RON 34 42 49 mΩ 1 A ≤ I(OUT) ≤ 5 A, TJ = 25°C 7
IN to OUT ON resistance RON RON 26 42 58 mΩ 1 A ≤ I(OUT) ≤ 5 A, -40°C ≤ TJ ≤ 85°C 7
IN to OUT ON resistance RON RON 26 42 64 mΩ 1 A ≤ I(OUT) ≤ 5 A, -40°C ≤ TJ ≤ 125°C 7
OUT leakage current in off state, sourcing Ilkg(OUT) -2 0 2 µA V(IN) = 18 V, V(EN/UVLO) = 0 V, V(OUT) = 0 V (Sourcing) 7
OUT leakage current in off state, sinking Ilkg(OUT) 6 13 20 µA V(IN) = 2.7 V, V(EN/UVLO) = 0 V, V(OUT) = 18 V (Sinking) 7
V(IN) - V(OUT) threshold for reverse protection comparator, falling V(REVTH) -15 -9.3 -3 mV 7
V(IN) - V(OUT) threshold for reverse protection comparator, rising V(FWDTH) 86 100 114 mV 7
FLT internal pull-down resistance R(FLT) 10 18 30 Ω V(OVP) = 2 V, I(FLT) = 5 mA sinking 7
PGTH threshold voltage, rising V(PGTHR) 0.97 0.99 1.01 V 7
PGTH threshold voltage, falling V(PGTHF) 0.9 0.92 0.94 V 7
PGOOD internal pull-down resistance R(PGOOD) 10 20 35 Ω V(PGTH) = 0V, I(PGOOD) = 5 mA sinking 7
Output ramp time tdVdT 0.25 0.37 0.5 ms EN/UVLO ↑ to V(OUT) = 11 V, with C(dVdT) = open 8
PGOOD delay (de-glitch) time, rising edge tPGOODR 0.42 0.54 0.66 ms Rising edge 8
Junction-to-ambient thermal resistance RθJA 38.1 °C/W 5
Junction-to-case (top) thermal resistance RθJCtop 40.5 °C/W 5
Junction-to-board thermal resistance RθJB 13.6 °C/W 5
Junction-to-case (bottom) thermal resistance RθJCbot 3.4 °C/W 5

CAD (KiCad official)

  • Symbol: TPS25940ARVCT
  • Footprint: Package_DFN_QFN:QFN-20-1EP_3x4mm_P0.5mm_EP1.65x2.65mm
  • 3D model: WQFN-20(4x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 2afef30f449360cd, retrieved 2026-10-30, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF