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TPS25840QWRHBRQ1

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Texas Instruments Power Management - Specialized, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TPS25840QWRHBRQ1

Texas Instruments · Power Management - Specialized · VQFN-32(5x5)

TPS25840QWRHBRQ1 from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input supply pin; operating range 4.5 V to 36 V with high-quality bypass capacitors to PGND.
2 IN power_in Input supply pin; operating range 4.5 V to 36 V with high-quality bypass capacitors to PGND.
3 IN power_in Input supply pin; operating range 4.5 V to 36 V with high-quality bypass capacitors to PGND.
4 EN/UVLO input Enable/UVLO control input with precision thresholds 1.2 V rising and 0.3 V falling, supporting external resistor divider for system protection.
5 CTRL1 input Logic-level mode configuration input (0 to VCC) combining with CTRL2 to select SDP, CDP, or Client operating mode.
6 CTRL2 input Logic-level mode configuration input (0 to VCC) combining with CTRL1 to select SDP, CDP, or Client operating mode.
7 DP_OUT output DP data line output to USB host controller with 800 MHz bandwidth analog switch for D+ differential signal routing.
8 DM_OUT output DM data line output to USB host controller with 800 MHz bandwidth analog switch for D- differential signal routing.
9 RT/SYNC input Resistor timing or external clock synchronization input supporting 300 kHz to 2.3 MHz frequency range via external RT resistor or AC-coupled clock.
10 LS_GD output Low-side NFET gate driver output providing 2-4 µA source current at 9.5-12.5 V for external current limit FET control.
11 IMON input Cable compensation monitor input with external RIMON resistor setting compensation voltage from 0 V to 1.5 V maximum.
12 ILIMIT input Current limit threshold input with external RILIMIT resistor setting average or NFET-based current limit threshold.
13 CSN/OUT power_out Buck regulator regulated output nominally 5.1 V ±1% (5.05 V to 5.15 V) and current sense amplifier negative input.
14 CSP input Current sense amplifier positive input monitoring voltage drop across external RSNS sense resistor for load current feedback.
15 BUS input VBUS input from USB connector with operating range 0 to 18 V and 7 V overvoltage protection threshold.
16 AGND power_in Analog ground reference for precision internal circuits and all electrical parameter measurements with respect to this pin.
17 DM_IN input DM data line input from USB connector with 800 MHz bandwidth, IEC 61000-4-2 ESD protection (±15 kV air discharge), and 3.9 V overvoltage threshold.
18 DP_IN input DP data line input from USB connector with 800 MHz bandwidth, IEC 61000-4-2 ESD protection (±15 kV air discharge), and 3.9 V overvoltage threshold.
19 N/C unconnected No electrical connection; must not be connected in application circuit.
20 INT input Internal circuit reference node requiring 5.1 kΩ external resistor connection to AGND for proper operation.
21 VCC power_out Internal LDO regulated bias supply output nominally 5 V (4.75 V to 5.25 V) requiring 2.2 µF minimum bypass capacitance to ground.
22 N/C unconnected No electrical connection; must not be connected in application circuit.
23 BUCK_ST tri_state Active-low open-drain buck converter start-up status output asserting after 150 ms soft-start and deglitch time.
24 FAULT tri_state Active-low open-drain fault status output asserts on overcurrent, overvoltage, or short circuit conditions with 8 ms typical deglitch.
25 PGND power_in Power ground return terminal connected to system ground plane and AGND via short wide traces.
26 PGND power_in Power ground return terminal connected to system ground plane and AGND via short wide traces.
27 PGND power_in Power ground return terminal connected to system ground plane and AGND via short wide traces.
28 SW output Buck regulator switching output node transitioning between 0 and VIN with 105 ns minimum on-time, connected to power inductor.
29 SW output Buck regulator switching output node transitioning between 0 and VIN with 105 ns minimum on-time, connected to power inductor.
30 SW output Buck regulator switching output node transitioning between 0 and VIN with 105 ns minimum on-time, connected to power inductor.
31 SW output Buck regulator switching output node transitioning between 0 and VIN with 105 ns minimum on-time, connected to power inductor.
32 BOOT passive Bootstrap capacitor connection for high-side FET driver; connect 0.1 µF high-quality ceramic X7R/X5R capacitor between this pin and SW.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS25840QWRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: tps25840qwrhbrq1-etched.step / tps25840qwrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps25840qwrhbrq1.step / tps25840qwrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (63 pp, sha256 7fdd561732d359bc, retrieved 2026-09-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF