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TPS25751SRSMR

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TEXAS INSTRUMENTS Power Management - Specialized, VQFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS25751SRSMR

TEXAS INSTRUMENTS · Power Management - Specialized · VQFN-32-EP(4x4)

TPS25751SRSMR from TEXAS INSTRUMENTS, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDO_3V3 power_out Output of the supply switched from VIN_3V3 or the VBUS LDO; bypass with capacitance CLDO_3V3 to GND.
2 ADCIN1 input Configuration input; connect to a resistor divider to LDO_3V3.
3 ADCIN2 input Configuration input; connect to a resistor divider to LDO_3V3.
4 LDO_1V5 power_out Output of the CORE LDO; bypass with capacitance CLDO_1V5 to GND, and the pin cannot source current to external circuits.
5 GPIO0 bidirectional General-purpose digital I/O; tie to ground when the pin is unused.
6 GPIO1 bidirectional General-purpose digital I/O; tie to ground when the pin is unused.
7 GPIO2 bidirectional General-purpose digital I/O; tie to ground when the pin is unused.
8 I2Ct_SDA bidirectional I2C target serial data, open-drain input/output; tie to a pull-up voltage through a resistor, or it may be grounded if unused.
9 I2Ct_SCL input I2C target serial clock input; tie to a pull-up voltage through a resistor, or it may be grounded if unused.
10 I2Ct_IRQ output I2C target interrupt, active low; connect to an external voltage through a pull-up resistor, can be reconfigured as GPIO10, and tie to ground when unused.
11 GND power_in Ground; connect to the ground plane.
12 GND power_in Ground; connect to the ground plane.
13 GPIO11 bidirectional General-purpose digital I/O; tie to ground when the pin is unused.
14 GND power_in Ground; connect to the ground plane.
15 I2Cc_SDA bidirectional I2C controller serial data, open-drain input/output; tie to a pull-up voltage through a resistor when used or unused.
16 I2Cc_SCL output I2C controller serial clock, open-drain output; tie to a pull-up voltage through a resistor when used or unused.
17 I2Cc_IRQ input I2C controller interrupt, active low; connect to an external voltage through a pull-up resistor, do not tie to GND when unused, and it can be reconfigured as GPIO12.
18 GPIO3 bidirectional General-purpose digital I/O; tie to ground when the pin is unused.
19 VSYS input High-voltage sinking node used to implement reverse-current protection (RCP) for the external sinking paths controlled by GATE_VSYS.
20 GATE_VSYS output Connects to the N-channel MOSFET whose source is tied to VSYS.
21 GATE_VBUS output Connects to the N-channel MOSFET whose source is tied to VBUS.
22 GPIO4/USB_P/LD1 bidirectional General-purpose digital I/O that can be connected to D+ for BC1.2 support or for liquid detection on the Type-C connector; tie to ground when unused.
23 GPIO5/USB_N/LD2 bidirectional General-purpose digital I/O that can be connected to D- for BC1.2 support or for liquid detection on the Type-C connector; tie to ground when unused.
24 CC1 bidirectional I/O for USB Type-C; filter noise with the recommended capacitor to GND (CCCy).
25 CC2 bidirectional I/O for USB Type-C; filter noise with the recommended capacitor to GND (CCCy).
26 VBUS power_in 5-V to 20-V input; bypass with capacitance CVBUS to GND.
27 VBUS power_in 5-V to 20-V input; bypass with capacitance CVBUS to GND.
28 PP5V power_in 5-V system supply to VBUS and supply for the CCy pins as VCONN.
29 PP5V power_in 5-V system supply to VBUS and supply for the CCy pins as VCONN.
30 GPIO7 bidirectional General-purpose digital I/O; tie to ground when the pin is unused.
31 GPIO6 bidirectional General-purpose digital I/O; tie to ground when the pin is unused.
32 VIN_3V3 power_in Supply for core circuitry and I/O; bypass with capacitance CVIN_3V3 to GND.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer TEXAS INSTRUMENTS
Package VQFN-32-EP(4x4)
Category Power Management (PMIC)
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range PP5V PP5V -0.3 6 V 7
Input voltage range VIN_3V3 VIN_3V3 -0.3 4 V 7
Input voltage range ADCIN1, ADCIN2 ADCIN1, ADCIN2 -0.3 4 V 7
Input voltage range VBUS_IN, VBUS VBUS_IN, VBUS -0.3 28 V 7
Input voltage range CC1, CC2 CC1, CC2 -0.5 26 V 7
Input voltage range GPIOx GPIOx -0.3 6 V 7
Input voltage range I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ, I2Ct_SCL, I2Ct_SDA I2Cc_SDA, I2Cc_SCL, I2Cc_IRQ, I2Ct_IRQ, I2Ct_SCL, I2Ct_SDA -0.3 4 V 7
Output voltage range LDO_1V5 LDO_1V5 -0.3 2 V 7
Output voltage range LDO_3V3 LDO_3V3 -0.3 4 V 7
Positive source current on CC1, CC2 1 A 7
Positive sink current on CC1, CC2 while VCONN switch is enabled 1 A VCONN switch enabled 7
Source current GPIOx GPIOx 0.005 A 7
Operating junction temperature TJ TJ -40 175 °C 7
Storage temperature TSTG TSTG -55 150 °C 7
Output voltage range GATE_VBUS, GATE_VSYS GATE_VBUS, GATE_VSYS -0.3 40 V 8
Gate-to-source voltage VGATE_VBUS - VVBUS, VGATE_SYS - VVSYS VGS -0.5 12 V 8
Input voltage range VIN_3V3 VIN_3V3 3 3.6 V 8
Input voltage range PP5V PP5V 4.9 5.5 V 8
Input voltage range VBUS VBUS 4 22 V 8
Input voltage range VSYS VSYS 0 22 V 8
I/O voltage range I2Cx_SDA, I2Cx_SCL, I2Cx_IRQ, ADCIN1, ADCIN2 VIO 0 3.6 V 8
I/O voltage range GPIOx VIO 0 5.5 V 8
I/O voltage range CC1, CC2 VIO 0 5.5 V 8
IO output current from PP5V to VBUS IO 3 A 8
IO output current from PP5V to CC1, CC2 IO 315 mA 8
IO output current from LDO_3V3 to GPIOx IO 1 mA 9
IO output current from VBUS LDO, sum of current from LDO_3V3 and GPIOx IO 5 mA 9
Operating junction temperature TJ TJ -40 125 °C 9
VBUS UVLO threshold, rising VVBUS_UVLO 3.6 3.9 V rising 11
VBUS UVLO threshold, falling VVBUS_UVLO 3.5 3.8 V falling 11
Voltage required on VIN_3V3 for power on, rising VVIN3V3_UVLO 2.56 2.66 2.76 V rising, VVBUS = 0 11
Voltage required on VIN_3V3 for power on, falling VVIN3V3_UVLO 2.44 2.54 2.64 V falling, VVBUS = 0 11
Voltage on LDO_3V3 VLDO_3V3 3 3.4 3.6 V VVIN_3V3 = 0 V, 10 µA ≤ ILOAD ≤ 18 mA, VBUS ≥ 3.9 V 11
Voltage on LDO_1V5 VLDO_1V5 1.49 1.5 1.65 V up to maximum internal loading condition 11
Resistance from PP5V to VBUS at 25 °C RPP_5V 36 38 mΩ ILOAD = 3 A, TJ = 25°C 11
Resistance from PP5V to VBUS at 125 °C RPP_5V 36 53 mΩ ILOAD = 3 A, TJ = 125°C 11
VBUS to PP5V leakage current IPP5V_REV 5 µA VPP5V = 0 V, VVBUS = 5.5 V, PP_5V disabled, TJ ≤ 85°C, measure IPP5V 11
PP5V to VBUS leakage current IPP5V_FWD 15 µA VPP5V = 5.5 V, VVBUS = 0 V, PP_5V disabled, TJ ≤ 85°C, measure IVBUS 11
Current limit setting 0 ILIM5V 1.15 1.36 A Configure to setting 0 11
Current limit setting 1 ILIM5V 1.61 1.9 A Configure to setting 1 11
Current limit setting 2 ILIM5V 2.3 2.7 A 11
Current limit setting 3 ILIM5V 3.04 3.58 A Configure to setting 3 11
Current limit setting 4 ILIM5V 3.22 3.78 A Configure to setting 4 12
PP_5V RCP threshold, VBUS - PP5V VPP_5V_RCP 10 20 mV Measure VVBUS, VPP5V 12
Comparator mode RCP threshold VVSYS - VVBUS, setting 0 VRCP 2 6 10 mV Setting 0, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 13
Comparator mode RCP threshold VVSYS - VVBUS, setting 1 VRCP 4 8 12 mV Setting 1, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 13
Comparator mode RCP threshold VVSYS - VVBUS, setting 2 VRCP 6 10 14 mV Setting 2, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 13
Comparator mode RCP threshold VVSYS - VVBUS, setting 3 VRCP 8 12 16 mV Setting 3, 4 V ≤ VVBUS ≤ 22 V, VVIN_3V3 ≤ 3.63 V 13
Soft start slew rate for GATE_VSYS, setting 0 SS 0.35 0.41 0.47 V/ms 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF 13
Soft start slew rate for GATE_VSYS, setting 1 SS 0.67 0.81 0.91 V/ms 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF 13
Soft start slew rate for GATE_VSYS, setting 2 SS 1.33 1.7 1.8 V/ms 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF 13
Soft start slew rate for GATE_VSYS, setting 3 SS 2.8 3.3 3.8 V/ms 4 V ≤ VVBUS ≤ 22 V, ILOAD = 100 mA, 500 pF < CGATE_VSYS < 16 nF 13
Current into VIN_3V3, Active Source mode IVIN_3V3,ActSrc 3 mA Active Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 11
Current into VIN_3V3, Active Sink mode IVIN_3V3,ActSnk 3 6 mA Active Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 11
Current into VIN_3V3, Idle Source mode IVIN_3V3,IdlSrc 1 mA Idle Source mode: VVBUS = 5.0 V, VVIN_3V3 = 3.3 V 11
Current into VIN_3V3, Idle Sink mode IVIN_3V3,IdlSnk 1 mA Idle Sink mode: 22 V ≥ VVBUS ≥ 4.0 V, VVIN_3V3 = 3.3 V 11
Current into PP5V in Sleep mode IPP5V,Sleep 2 µA Sleep mode: VPA_VBUS = 0 V, VVIN_3V3 = 3.3 V 11
Current into VIN_3V3 in Sleep mode IVIN_3V3,Sleep 56 µA Sleep mode: VVBUS = 0 V, VVIN_3V3 = 3.3 V 11
Junction-to-ambient thermal resistance RθJA 30.5 °C/W 10
Junction-to-board thermal resistance RθJB 9.8 °C/W 10

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper pins (pins 15 and 30) to the Drain pad underneath the TPS25751D device. Connect the through hole vias from the drain pad on the top layer to a copper pour on the bottom layer to help dissipate heat. A 67

CAD (KiCad official)

  • Symbol: TPS25751SRSMR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps25751srsmr-etched.step / tps25751srsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps25751srsmr.step / tps25751srsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TEXAS INSTRUMENTS datasheet (88 pp, sha256 1cbfd53db9072862, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF