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TPS25741ARSMT

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Texas Instruments Power Management - Specialized, VQFN-32(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TPS25741ARSMT

Texas Instruments · Power Management - Specialized · VQFN-32(4x4)

TPS25741ARSMT from Texas Instruments, in a VQFN-32(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VTX power_out Bypass pin for the transmit driver supply; use a 0.1 µF ceramic capacitor.
2 CC1 bidirectional Multifunction USB Type-C configuration channel pin for connector polarity, end-device connection detect, current capability and Power Delivery communication, with sustained pin voltage limited to -0.3 V to 6 V.
3 VCONN power_in Input for the VCONN supply, internally current limited and routed to the CC pin not connected to the cable once UFP is pulled low; bypass to GND with the recommended capacitor and keep sustained voltage within -0.3 V to 7 V.
4 CC2 bidirectional Multifunction USB Type-C configuration channel pin for connector polarity, end-device connection detect, current capability and Power Delivery communication, with sustained pin voltage limited to -0.3 V to 6 V.
5 GND power_in Power ground for power management and gate driver circuits; connect to AGND and the thermal pad.
6 HIPWR input Four-state input that sets the voltages and currents advertised, connected directly to GND or DVDD or through resistance RSEL, with pin voltage limited to -0.3 V to 2.1 V.
7 CTL1 output Digital output used to control an external voltage regulator, with average sink current limited to 8 mA.
8 CTL2 output Digital output used to control an external voltage regulator, with average sink current limited to 8 mA.
9 POL output Goes low when a UFP is connected on CC2 and is high-impedance otherwise; average sink current limited to 8 mA.
10 EN9V/EN12V input On TPS25741 this enables the 12 V PDO when pulled high (not advertised when low); on TPS25741A it enables the 9 V PDO in the same way.
11 N/C passive Datasheet states this pin is to be connected to GND.
12 N/C passive Datasheet states this pin is to be connected to GND.
13 N/C passive Datasheet states this pin is to be connected to GND.
14 UFP output Goes low to indicate that either CC1 or CC2 (but not both) is pulled down by a USB Type-C Sink; average sink current limited to 8 mA.
15 DEBUG output Goes low when a debug accessory is present and is high-impedance otherwise; average sink current limited to 8 mA.
16 PSEL input Four-state input that selects the maximum power that can be provided, connected directly to GND or DVDD or through resistance RSEL, with pin voltage limited to -0.3 V to 2.1 V.
17 VIO input Connect VIO to the DVDD pin; sustained pin voltage limited to -0.3 V to 6 V.
18 DVDD power_out Internally regulated 1.85 V rail for external use up to 35 mA; connect to GND via the recommended bypass capacitor.
19 PCTRL input Input that controls the power advertised and may be pulled high or low dynamically; sustained pin voltage limited to -0.3 V to 6 V.
20 GD input Master enable for the GDNG/GDNS gate drivers; driving it low forces the power path switch off, with sustained pin voltage limited to -0.3 V to 7 V.
21 VAUX power_out Internally regulated rail for the power management circuits; connect to GND via the recommended bypass capacitor.
22 VDD power_in Optional input supply; sustained pin voltage limited to -0.3 V to 6 V.
23 AGND power_in Analog ground for monitoring and power-conditioning circuits; connect to GND and the thermal pad.
24 ISNS input Monitors a VBUS-referenced sense resistor for over-current events; ISNS-to-VBUS voltage limited to ±0.3 V and sustained pin voltage to -0.5 V to 30 V.
25 VPWR power_in Bias power input from an external voltage source; optional while UFP is high if VDD is supplied, with sustained pin voltage limited to -0.5 V to 30 V.
26 VBUS power_in Voltage monitor for the USB connector VBUS line, which is the high-side power conductor; sustained pin voltage limited to -0.5 V to 30 V.
27 GDPG output High-voltage open-drain gate driver that may drive PMOS power switches; pin voltage limited to -0.3 V to 30 V and average sink current to 3.5 mA.
28 AUDIO output Goes low when an audio accessory is present and is high-impedance otherwise; average sink current limited to 3.5 mA.
29 GDNG output High-voltage open-drain gate driver for NMOS power switches, connected to the gate terminal; V(GDNG)-V(GDNS) limited to -0.3 V to 20 V.
30 GDNS output High-voltage open-drain gate driver for NMOS power switches, connected to the source terminal; sustained pin voltage limited to -0.5 V to 30 V.
31 DSCG output Open-drain output that discharges the system VBUS line through an external resistor; average sink current limited to 10 mA and sustained pin voltage to -0.5 V to 30 V.
32 G5V output Analog gate drive output for an external NMOS power switch; sustained pin voltage limited to -0.3 V to 20 V.
33 PAD passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(4x4)
Category Power Management (PMIC)
Pins 33

CAD (KiCad official)

  • Symbol: TPS25741ARSMT
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps25741arsmt-etched.step / tps25741arsmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps25741arsmt.step / tps25741arsmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (69 pp, sha256 c9e2a2d29126c712, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF