component
TPS25740RGER
Public Made by Adomby adom
Texas Instruments USB ICs, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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| tps25740rger-etched.glb | 18h ago |
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TPS25740RGER
Texas Instruments · USB ICs · VQFN-24-EP(4x4)
TPS25740RGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VTX | power_out | Bypass pin for the transmit driver supply, to be connected to GND via the recommended ceramic capacitor. |
| 2 | CC1 | bidirectional | Multifunction configuration channel interface pin to USB Type-C providing connector polarity, end-device connection detect, current capability and PD communication. |
| 3 | CC2 | bidirectional | Multifunction configuration channel interface pin to USB Type-C providing connector polarity, end-device connection detect, current capability and PD communication. |
| 4 | GND | power_in | Power ground associated with power management and gate driver circuits, to be connected to AGND and PAD. |
| 5 | HIPWR | input | Four-state input used to configure the voltages and currents that will be advertised, connected directly to GND or DVDD or via a resistance R(SEL). |
| 6 | CTL1 | output | Digital output pin used to control an external voltage regulator. |
| 7 | CTL2 | output | Digital output pin used to control an external voltage regulator. |
| 8 | EN12V / EN9V | input | For TPS25740 a low level allows the 12 V PDO to be transmitted and for TPS25740A it allows the 9 V PDO to be transmitted; if not pulled low the corresponding PDO is not advertised. |
| 9 | N/C | passive | Not internally used; the datasheet states to connect this pin to GND. |
| 10 | N/C | passive | Not internally used; the datasheet states to connect this pin to GND. |
| 11 | UFP | output | Open-drain output indicating that either CC1 or CC2 (but not both) is pulled down by a USB Type-C Sink. |
| 12 | PSEL | input | Four-state input used to select the maximum power that can be provided, connected directly to GND or DVDD or via a resistance R(SEL). |
| 13 | DVDD | power_out | Internally regulated 1.85 V rail for external use up to 35 mA, to be connected to GND via the recommended bypass capacitor. |
| 14 | PCTRL | input | Input pin used to control the power that will be advertised, and it may be pulled high or low dynamically. |
| 15 | GD | input | Master enable for the GDNG/GDNS gate driver; driving it low forces the power path switch off. |
| 16 | VAUX | power_out | Internally regulated rail for use by the power management circuits, to be connected to GND via the recommended bypass capacitor. |
| 17 | VDD | power_in | Optional input supply. |
| 18 | AGND | power_in | Analog ground associated with monitoring and power conditioning circuits, to be connected to GND and PAD. |
| 19 | ISNS | input | Used to monitor a VBUS-referenced sense resistor for over-current events. |
| 20 | VPWR | power_in | Connect to an external voltage as a source of bias power; this supply is optional while UFP is high if VDD is supplied. |
| 21 | VBUS | power_in | Voltage monitor for the VBUS line. |
| 22 | GDNG | output | High-voltage open-drain gate driver which may be used to drive NMOS power switches, connected to the gate terminal. |
| 23 | GDNS | input | High-voltage open-drain gate driver which may be used to drive NMOS power switches, connected to the source terminal. |
| 24 | DSCG | output | Open-drain output that discharges the system VBUS line through an external resistor. |
| 25 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Pin voltage (sustained): VDD, EN12V, EN9V, CTL1, CTL2, UFP, PCTRL, CC1, CC2 | -0.3 | 6 | V | 6 | |||
| Pin voltage (sustained): VTX | -0.3 | 2.1 | V | 6 | |||
| Pin voltage (sustained): VAUX | -0.3 | 4.5 | V | 6 | |||
| Pin voltage (sustained): GD | -0.3 | 7 | V | 6 | |||
| Pin voltage (sustained): HIPWR, PSEL, DVDD | -0.3 | 2.1 | V | 6 | |||
| Pin voltage (sustained): GDNG | -0.5 | 40 | V | 6 | |||
| Pin voltage (sustained): VBUS, VPWR, ISNS, DSCG, GDNS | -0.5 | 30 | V | 6 | |||
| Pin voltage (transient): VBUS, VPWR, ISNS, DSCG, GDNS | -1.5 | 30 | V | transient for 1 ms | 6 | ||
| Pin-to-pin voltage V(GDNG), V(GDNS) | V(GDNG), V(GDNS) | -0.3 | 20 | V | 6 | ||
| AGND to GND | -0.3 | 0.3 | V | 6 | |||
| ISNS to VBUS | -0.3 | 0.3 | V | 6 | |||
| Sinking current (average): CTL1, CTL2, UFP | 8 | mA | 6 | ||||
| Sinking current: GD | 100 | µA | 6 | ||||
| Sinking current (average): DSCG | 10 | mA | 6 | ||||
| Sinking current (transient): DSCG | 375 | mA | 50 ms pulse, 0.25% duty cycle | 6 | |||
| Current sourcing: VAUX | 0 | 25 | µA | 6 | |||
| Operating junction temperature range | TJ | -40 | 125 | °C | 6 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| VIN supply voltage: VDD | VDD | 0 | 5.5 | V | 7 | ||
| VIN supply voltage: VPWR | VPWR | 4.65 | 25 | V | 7 | ||
| Applied voltage: EN12V, EN9V, PCTRL, CC1, CC2, CTL1, CTL2 | VI | 0 | 5.5 | V | 7 | ||
| Applied voltage: GD | VI | 0 | 6.5 | V | 7 | ||
| Applied voltage: DSCG, GDNS, VBUS | VI | 0 | 25 | V | 7 | ||
| Pin-to-pin voltage ISNS - VBUS | VI | -0.1 | 0.1 | V | 7 | ||
| High-level input voltage: EN12V, EN9V | VIH | 1.4 | V | 7 | |||
| High-level input voltage: PCTRL | VIH | 2 | V | 7 | |||
| Low-level input voltage: EN12V, EN9V | VIL | 0.5 | V | 7 | |||
| Low-level input voltage: PCTRL | VIL | 1.6 | V | 7 | |||
| Sinking current: CTL1, CTL2, UFP | IS | 5 | mA | 7 | |||
| Sinking current: DSCG transient | IS | 350 | mA | 50 ms pulse, 0.25% duty cycle | 7 | ||
| CC1, CC2 shunt capacitance (C(RX)) | C(RX) | 200 | 560 | 600 | pF | 7 | |
| DVDD bypass capacitance (C(DVDD)) | C(DVDD) | 0.198 | 0.22 | 0.242 | µF | 7 | |
| Sense resistance configured for 3 A | RS | 5 | 6.4 | mΩ | 7 | ||
| Sense resistance configured for 5 A | RS | 5 | 5.8 | mΩ | 7 | ||
| Pull up/down resistance: HIPWR, PSEL (direct to GND or direct to DVDD) | R(PUD) | 0 | 1 | kΩ | 7 | ||
| Pull up/down resistance: HIPWR, PSEL (R(SEL)) | R(SEL) | 80 | 100 | 120 | kΩ | 7 | |
| Voltage Comparator (VBUS): VBUS threshold (rising voltage) | V(VBUS_RTH) | 4.25 | 4.45 | 4.65 | V | 8 | |
| Voltage Comparator (VBUS): VBUS threshold (falling voltage) | V(VBUS_FTH) | 3.5 | 3.7 | 3.9 | V | 8 | |
| VDD UVLO threshold | V(VDD_TH) | 2.8 | 2.91 | 2.97 | V | Rising voltage | 8 |
| VPWR UVLO threshold rising | V(VPWR_RTH) | 4.2 | 4.45 | 4.65 | V | Rising voltage | 8 |
| VPWR UVLO threshold falling | V(VPWR_FTH) | 3.5 | 3.7 | 3.9 | V | Falling voltage | 8 |
| Fast OVP threshold, always enabled | V(FOVP) | 5.8 | 6.05 | 6.3 | V | 5 V PD contract | 8 |
| Fast OVP threshold, always enabled | V(FOVP) | 13.2 | 13.75 | 14.3 | V | 12 V PD contract (TPS25740) | 8 |
| Fast OVP threshold, always enabled | V(FOVP) | 22.1 | 23.05 | 24 | V | 20 V PD contract (TPS25740) | 8 |
| Slow OVP threshold, disabled during voltage transitions | V(SOVP) | 13.1 | 13.4 | 13.7 | V | 12 V PD contract (TPS25740) | 8 |
| UVP threshold, disabled during voltage transitions | V(SUVP) | 9.2 | 9.45 | 9.7 | V | 12 V PD contract (TPS25740) | 8 |
| VAUX output voltage | V(VAUX) | 2.875 | 3.2 | 4.1 | V | 0 ≤ I(VAUX) ≤ I(VAUXEXT) | 8 |
| DVDD output voltage | V(DVDD) | 1.75 | 1.85 | 1.95 | V | 0 mA ≤ I(DVDD) ≤ 35 mA, CC1 or CC2 pulled to ground via 5.1 kΩ, or both CC1 and CC2 pulled to ground via 1 kΩ | 8 |
| VTX output voltage | V(VTX) | 1.05 | 1.125 | 1.2 | V | Not transmitting or receiving, 0 to 2 mA external load | 9 |
| Gate Driver Disable (GD) input enable threshold voltage | V(GD_TH) | 1.64 | 1.725 | 1.81 | V | Rising voltage | 9 |
| N-ch MOSFET gate driver sourcing voltage while enabled (V(GDNG)-V(GDNS)) | V(GDNON) | 7 | 12 | V | 0 V ≤ V(GDNS) ≤ 25 V, I(GDNON) ≤ 4 µA, VPWR = 0 V | 9 | |
| Power Control Input (PCTRL) threshold voltage | V(PCTRL_TH) | 1.65 | 1.75 | 1.85 | V | Voltage rising | 9 |
| Supply current drawn from VDD in sleep mode | 9.2 | 20 | µA | VPWR = 0 V, VDD = 5 V, CC1 and CC2 pins are open. | 8 | ||
| I(SUPP) operating current while sink attached | I(SUPP) | 1 | 1.8 | 3 | mA | PD Sourcing active, VBUS = 5 V, VPWR = 5 V, VDD = 3.3 V | 8 |
| N-ch MOSFET gate driver sourcing current | I(GDNON) | 13.2 | 20 | 30 | µA | 0 V ≤ V(GDNS) ≤ 25 V, 0 V ≤ V(GDNG), V(GDNS) ≤ 6 V | 9 |
| Output low voltage (CTL1, CTL2, UFP) | VOL | 0.4 | V | IOL = 4 mA sinking | 9 | ||
| Discharge (DSCG) ON state (linear) | V(DSCGT) | 0.15 | 0.42 | 1 | V | I(DSCG) = 100 mA | 9 |
| Transmit high voltage (CC1, CC2) | V(TXHI) | 1.05 | 1.125 | 1.2 | V | External Loading per Figure 25 | 10 |
| Junction-to-ambient thermal resistance (RGE 24-pin VQFN) | RθJA | 33 | °C/W | 7 | |||
| Junction-to-board thermal resistance (RGE 24-pin VQFN) | RθJB | 10 | °C/W | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | • R(DSCG): Place on top of the VBUS copper route and connect to the DSCG pin with a 15 mil trace. | 56 |
CAD (KiCad official)
- Symbol:
TPS25740RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tps25740rger-etched.step/tps25740rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps25740rger.step/tps25740rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (66 pp, sha256
7e194c4d808d53a0, retrieved 2026-10-31, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).