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TPS25730SRSMR

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Texas Instruments USB PD, VQFN-32-EP(4x4). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps25730srsmr
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docs tps25730srsmr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
viewers tps25730srsmr: viewers · Ray 28d ago
package.json Publish 0.1.0 · Ray 28d ago
page.json tps25730srsmr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 18h ago
README.md tps25730srsmr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 16d ago
tps25730srsmr-etched.fit.json tps25730srsmr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tps25730srsmr-etched.glb tps25730srsmr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tps25730srsmr-etched.step tps25730srsmr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 5d ago
tps25730srsmr.glb Publish 0.1.0 · Ray 28d ago
tps25730srsmr.kicad_mod Publish 0.1.0 · Ray 28d ago
tps25730srsmr.kicad_sym Publish 0.1.0 · Ray 28d ago
tps25730srsmr.lbr Publish 0.1.0 · Ray 28d ago
tps25730srsmr.step Publish 0.1.0 · Ray 28d ago

TPS25730SRSMR

Texas Instruments · USB PD · VQFN-32-EP(4x4)

TPS25730SRSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 LDO_3V3 power_out Output of the supply switched from VIN_3V3 or VBUS LDO. Bypass to GND with CLDO_3V3.
2 ADCIN1 input Configuration input. Connect to a resistor divider to LDO_3V3 for pin-strap configuration. Hi-Z at reset.
3 ADCIN2 input Configuration input. Connect to a resistor divider to LDO_3V3 for pin-strap configuration. Hi-Z at reset.
4 LDO_1V5 power_out Output of the core LDO. Bypass with CLDO_1V5 to GND. Cannot source current to external circuits.
5 ADCIN3 input Configuration input. Connect to a resistor divider to LDO_3V3 for pin-strap configuration. Hi-Z at reset.
6 CAP_MIS output Open-drain output. Capability mismatch indicator: toggled = capability mismatch in negotiated PD contract; not toggled = no capability mismatch.
7 ADCIN4 input Configuration input. Connect to a resistor divider to LDO_3V3 for pin-strap configuration. Hi-Z at reset.
8 I2Ct_SDA bidirectional I2C target serial data (open-drain). Tie to pull-up voltage through a resistor; may be grounded if unused.
9 I2Ct_SCL input I2C target serial clock input. Tie to pull-up voltage through a resistor; may be grounded if unused.
10 DBG_ACC output Open-drain output. Debug accessory attached Rp/Rp or Rd/Rd. 1 = debug accessory present, 0 = no debug accessory.
11 GND power_in Ground. Connect to ground plane.
12 GND power_in Ground. Connect to ground plane.
13 PLUG_FLIP output Open-drain output. Cable plug orientation indicator: 1 = CC2 connected (upside-down), 0 = CC1 connected (upside-up).
14 GND power_in Ground. Connect to ground plane.
15 GND power_in Ground. Connect to ground plane.
16 GND power_in Ground. Connect to ground plane.
17 FAULT_IN input Active-low fault input to disconnect from the port. When powered from VBUS, this causes the PD controller to lose power when VBUS is removed. 0 = disconnect from port, 1 = maintain connection (no fault).
18 SINK_EN output Active-low open-drain output. Sink path enabled indicator; may be used to control an external load switch. 0 = sink path enabled, 1 = sink path disabled.
19 VSYS power_in High-voltage sinking node in the system. Used to implement reverse current protection (RCP) for the external sink path controlled by GATE_VSYS.
20 GATE_VSYS output High-voltage gate driver output. Connect to the N-channel MOSFET whose source is tied to VSYS (reverse current protection FET in the external sink path).
21 GATE_VBUS output High-voltage gate driver output. Connect to the N-channel MOSFET whose source is tied to VBUS (sink path FET).
22 RESERVED input Reserved. Tie to ground or LDO_3V3.
23 RESERVED input Reserved. Tie to ground or LDO_3V3.
24 CC1 bidirectional USB Type-C CC1 pin (CCcy). Filter noise with recommended capacitor to GND.
25 CC2 bidirectional USB Type-C CC2 pin (CCcy). Filter noise with recommended capacitor to GND.
26 VBUS power_in USB Type-C VBUS input to internal LDO, 5-V to 20-V range. Bypass with CVBUS to GND.
27 VBUS power_in USB Type-C VBUS input to internal LDO, 5-V to 20-V range. Bypass with CVBUS to GND.
28 GND power_in Ground. Connect to ground plane.
29 GND power_in Ground. Connect to ground plane.
30 RESERVED input Reserved. Tie to ground or LDO_3V3.
31 PLUG_EVENT output Open-drain output. 1 = connection present, 0 = no connection present.
32 VIN_3V3 power_in Supply for core circuitry and I/O (nominal 3.3 V). Bypass with CVIN_3V3 to GND.
33 GND power_in Exposed thermal pad (GND). Connect to the ground plane for both electrical ground and heat dissipation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(4x4)
Category Power Management (PMIC)
Pins 33

Ordering variants

Same part, different packaging or reel option.

  • TPS25730SRSMR
  • TPS25730SRSMRDRFR
  • TPS25730SRSMRD

CAD (KiCad official)

  • Symbol: TPS25730SRSMR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: tps25730srsmr-etched.step / tps25730srsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps25730srsmr.step / tps25730srsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (71 pp, sha256 21ea4dc8b4aa380c, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF