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TPS2546RTET

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Texas Instruments Power Distribution Switches, WQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)tps2546rtetfactory-2.0.0extractor-text

Verified TPS2546RTET

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS2546RTET · WQFN-16-EP(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 44-page datasheet
  • ✓distributor: lcsc C205974, digikey 296-46468-2-ND, mouser 595-TPS2546RTET
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-_gdgwboa/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps2546rtet.kicad_sym✓ tps2546rtet.kicad_mod✓ tps2546rtet.step
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TPS2546RTET

Texas Instruments · Power Distribution Switches · WQFN-16-EP(3x3)

TPS2546RTET from Texas Instruments, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN power_in Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close to the device as possible.
2 DM_OUT bidirectional D- data line to USB host controller.
3 DP_OUT bidirectional D+ data line to USB host controller.
4 ILIM_SEL input Logic-level input signal used to control the charging mode, current limit threshold, and load detection; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
5 EN input Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the signal and power switches and holds OUT in discharge. Can be tied directly to IN or GND without pullup or pulldown resistor.
6 CTL1 input Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
7 CTL2 input Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
8 CTL3 input Logic-level input used to control the charging mode and the signal switches; see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
9 STATUS output Active-low open-drain output, asserted in load detection conditions.
10 DP_IN bidirectional D+ data line to downstream connector.
11 DM_IN bidirectional D- data line to downstream connector.
12 OUT power_out Power-switch output.
13 FAULT output Active-low open-drain output, asserted during overtemperature or current limit conditions.
14 GND power_in Ground connection.
15 ILIM_LO input External resistor connection used to set the low current-limit threshold and the load detection current threshold; a resistor to ILIM_LO is optional.
16 ILIM_HI input External resistor connection used to set the high-current-limit threshold.
17 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-16-EP(3x3)
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage IN, EN, ILIM_LO, ILIM_HI, FAULT, STATUS, ILIM_SEL, CTL1, CTL2, CTL3, OUT -0.3 7 V 4
Voltage IN to OUT -7 7 V 4
Voltage DP_IN, DM_IN, DP_OUT, DM_OUT -0.3 V max printed as (IN + 0.3) or 5.7 V 4
Input clamp current DP_IN, DM_IN, DP_OUT, DM_OUT -20 20 mA 4
Continuous current in SDP or CDP mode DP_IN to DP_OUT or DM_IN to DM_OUT -100 100 mA 4
Continuous current in BC1.2 DCP mode DP_IN to DM_IN -50 50 mA 4
Continuous output sink current FAULT, STATUS 25 mA 4
Operating junction temperature TJ TJ -40 °C max printed as Internally limited 4
Input voltage, IN VIN 4.5 5.5 V 4
Input voltage, logic-level inputs EN, CTL1, CTL2, CTL3, ILIM_SEL 0 5.5 V 4
Input voltage, data line inputs DP_IN, DM_IN, DP_OUT, DM_OUT 0 V max printed as VIN 4
High-level input voltage EN, CTL1, CTL2, CTL3, ILIM_SEL VIH 1.8 V 4
Low-level input voltage EN, CTL1, CTL2, CTL3, ILIM_SEL VIL 0.8 V 4
Continuous current, data line inputs, SDP or CDP mode -30 30 mA DP_IN to DP_OUT, DM_IN to DM_OUT 4
Continuous current, data line inputs, BC1.2 DCP mode -15 15 mA DP_IN to DM_IN 4
Continuous output current, OUT IOUT 0 2.5 A 4
Continuous output sink current, FAULT, STATUS 0 10 mA 4
Current-limit set resistors RILIM_XX 16.9 750 kΩ 4
Operating virtual junction temperature TJ -40 125 °C 4
ON resistance RDS(on) 73 84 mΩ TJ = 25°C, IOUT = 2 A 5
ON resistance RDS(on) 73 105 mΩ -40°C ≤ TJ ≤ 85°C, IOUT = 2 A 5
ON resistance RDS(on) 73 120 mΩ -40°C ≤ TJ ≤ 125°C, IOUT = 2 A 5
OUT voltage rise time tr 0.7 1 1.6 ms VIN = 5 V, CL = 1 µF, RL = 100 Ω 5
OUT voltage fall time tf 0.2 0.35 0.5 ms 5
OUT voltage turnon time ton 2.7 4 ms VIN = 5 V, CL = 1 µF, RL = 100 Ω 5
OUT voltage turnoff time toff 1.7 3 ms 5
OUT discharge resistance RDCHG 400 500 630 Ω 5
Long OUT discharge hold time tDCHG_L 1.3 2 2.9 s Time VOUT < 0.7 V 5
Short OUT discharge hold time tDCHG_S 205 310 450 ms Time VOUT < 0.7 V 5
Input pin rising logic threshold voltage 1 1.35 1.7 V 5
Input pin falling logic threshold voltage 0.85 1.15 1.45 V 5
Input current -0.5 0.5 µA Pin voltage = 0 V or 5.5 V 5
OUT short-circuit current limit IOS 205 240 275 mA VILIM_SEL = 0 V, RILIM_LO = 210 kΩ 5
OUT short-circuit current limit IOS 575 625 680 mA VILIM_SEL = 0 V, RILIM_LO = 80.6 kΩ 5
OUT short-circuit current limit IOS 2120 2275 2430 mA VILIM_SEL = 0 V, RILIM_LO = 22.1 kΩ 5
OUT short-circuit current limit IOS 2340 2510 2685 mA VILIM_SEL = VIN, RILIM_HI = 20 kΩ 5
OUT short-circuit current limit IOS 2770 2970 3170 mA VILIM_SEL = VIN, RILIM_HI = 16.9 kΩ 5
Disabled IN supply current IIN_OFF 0.1 2 µA VEN = 0 V, VOUT = 0 V, -40 ≤ TJ ≤ 85°C 6
Enabled IN supply current IIN_ON 165 220 µA VCTL1 = VCTL2 = VIN, VCTL3 = 0 V, VILIM_SEL = 0 V 6
Enabled IN supply current IIN_ON 175 230 µA VCTL1 = VCTL2 = VCTL3 = VIN, VILIM_SEL = 0 V 6
Enabled IN supply current IIN_ON 185 240 µA VCTL1 = VCTL2 = VIN, VCTL3 = 0 V, VILIM_SEL = VIN 6
Enabled IN supply current IIN_ON 195 250 µA VCTL1 = VCTL2 = VIN, VCTL3 = VIN, VILIM_SEL = VIN 6
Enabled IN supply current IIN_ON 215 270 µA VCTL1 = 0 V, VCTL2 = VCTL3 = VIN 6
IN rising UVLO threshold voltage VUVLO 3.9 4.1 4.3 V 6
FAULT output low voltage 100 mV IFAULT = 1 mA 6
FAULT OFF-state leakage 1 µA VFAULT = 5.5 V 6
Overcurrent FAULT rising and falling deglitch 5 8.2 12 ms 6
STATUS output low voltage 100 mV ISTATUS = 1 mA 6
STATUS OFF-state leakage 1 µA VSTATUS = 5.5 V 6
IREV Reverse leakage current IREV 2 µA VOUT = 5.5 V, VIN = VEN = 0 V, -40 ≤ TJ ≤ 85°C 5
DP/DM switch ON resistance 2 4 Ω VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA 6
DP/DM switch ON resistance 3 6 Ω VDP/DM_OUT = 2.4 V, IDP/DM_IN = -15 mA 6
Switch resistance mismatch between DP / DM channels 0.05 0.15 Ω VDP/DM_OUT = 0 V, IDP/DM_IN = 30 mA 6
DP/DM switch OFF-state capacitance 3 3.6 pF VEN= 0 V, VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz 6
DP/DM switch ON-state capacitance 5.4 6.2 pF VDP/DM_IN = 0.3 V, Vac = 0.6 Vpk-pk, f = 1 MHz 6
OFF-state leakage current 0.1 1.5 µA VEN = 0 V, VDP/DM_IN = 3.6 V, VDP/DM_OUT = 0 V 6
Skew between opposite transitions of the same port (tPHL, tPLH) tSK 0.1 0.2 ns 7
DP_IN / DM_IN shorting resistance 125 200 Ω VCTL1 = VIN, VCTL2 = VCTL3 = 0 V 7
DP_IN /DM_IN output voltage (1.2 V mode) 1.19 1.25 1.31 V VCTL1 = VIN, VCTL2 = VCTL3 = 0 V 7
Junction-to-ambient thermal resistance RθJA 53.4 °C/W 5

CAD (KiCad official)

  • Symbol: TPS2546RTET
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tps2546rtet-etched.step / tps2546rtet-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2546rtet.step / tps2546rtet.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (44 pp, sha256 2209637fcc33f6c4, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF