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TPS2492PW

Texas Instruments · Supervisor And Reset ICs · TSSOP-14

TPS2492PW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 UVEN input A low input inhibits GATE, the positive UVEN threshold must be exceeded before the GATE driver is enabled, and the pin can serve as a logic enable or an analog input voltage monitor.
2 VREF power_in Provides a 4.0-V reference voltage used to set the power threshold on PROG, and no more than 1 mA should be drawn from it.
3 PROG input FET power-limit programming pin, where the applied voltage (0.4 V minimum) sets the constant power limit and voltages greater than 4 V must not be applied.
4 TIMER bidirectional A capacitor from TIMER to ground sets the fault timer period, and the pin should be tied to ground if the timer feature is not used.
5 OV input Overvoltage sensing input where a high input inhibits GATE.
6 IMON output Analog current monitor output, nominally VIMON = 48 x (VVCC-SENSE), with a recommended sourcing current of up to 1.9 mA.
7 GND power_in Ground reference for the device.
8 PG output Active-low power-good open-drain output driven by VVCC-SENSE, with a sink current rating of 10 mA maximum for PG and FLT.
9 FLT output Active-low fault indicator open-drain output that goes low when the fault timer has expired and is reset by UVEN, UVLO, or automatic restart.
10 NC unconnected No connect pin.
11 OUT input FET source voltage sensing input used to measure VDS as V(SENSE-OUT), and a clamp diode to GND is needed if the load can drive OUT below ground, clamping it above -1 V.
12 GATE output Gate driver output for the external N-channel FET, with a 22 µA pull-up from the charge pump and strong (125 mA) and weak (2 mA) pull-downs, clamped to a diode drop below OUT.
13 SENSE input Monitors the downstream side of RSENSE and the FET drain for the constant power engine, with current limit clamped to 50 mV at low FET VDS and SENSE internally clamped to VCC.
14 VCC power_in Input supply and current sense positive input operating from 9 V to 80 V, which must exceed about 6 V POR and about 8 V UVLO before GATE operation begins.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Power Management (PMIC)
Pins 14

CAD (KiCad official)

  • Symbol: TPS2492PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: tps2492pw-etched.step / tps2492pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2492pw.step / tps2492pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 5a3953974c9098a7, retrieved 2026-10-11, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF