component
TPS2480PW
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TPS2480PW
Texas Instruments · Supervisor And Reset ICs · TSSOP-20
TPS2480PW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA | bidirectional | I2C data line for the TPS2480/81 interface, with data input from the I2C bus. |
| 2 | SCL | input | I2C clock input for the TPS2480/81 interface. |
| 3 | NC | unconnected | No internal connection; tie to GND or float. |
| 4 | VS | power_in | Power input to the I2C block, 3.3 V to 5 V, used as the power source for the logic and I2C interface. |
| 5 | NC | unconnected | No connection; tie to GND or float. |
| 6 | EN | input | Device enable input; the GATE driver is enabled only when the positive threshold is exceeded and the internal POR and UVLO thresholds are satisfied. |
| 7 | VREF | power_in | Reference voltage output of 4.0 V used with a resistor divider to set the PROG pin voltage; no more than 1 mA may be drawn. |
| 8 | PROG | input | Power-limit setting input; the applied voltage must stay within 0.4 V to 4.0 V and must not exceed 4 V. |
| 9 | TIMER | passive | Fault timing capacitor pin; the timer charges at 25 mA and discharges at 2.5 mA, and the pin should be tied to ground if the feature is not used. |
| 10 | GND | power_in | System ground. |
| 11 | PG | output | Open-drain power good output that goes high-impedance after the external FET VDS falls to about 1.25 V and a 9-ms deglitch period has elapsed. |
| 12 | OUT | input | Output voltage feedback input used to measure the external FET VDS as V(SENSE-OUT). |
| 13 | GATE | output | High-side gate drive output for the external N-channel FET, with a 22 mA pull-up and a 75 mA (min) pull-down. |
| 14 | SENSE | input | Current-limit sense input monitoring the drain of the external FET and RS; it is internally clamped to VCC, so it must not be driven to a large voltage difference from VCC. |
| 15 | VCC | power_in | Main power supply input to the device and FET; it must exceed the POR (about 6 V) and UVLO (about 8 V) thresholds before normal operation. |
| 16 | GND | power_in | System ground. |
| 17 | VINP | input | Positive differential shunt voltage input, Kelvin connected to the positive side of the current sensing resistor. |
| 18 | VINM | input | Negative differential shunt voltage input, Kelvin connected to the negative side of the current sensing resistor; bus voltage is measured from this pin to GND. |
| 19 | A1 | input | Address pin for setting the I2C address, tied to GND, SDA, SCL or VS as shown in Table 2. |
| 20 | A0 | input | Address pin for setting the I2C address, tied to GND, SDA, SCL or VS as shown in Table 2. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC input voltage range | VCC | 9 | 80 | V | 2 | ||
| PROG input voltage range | PROG | 0.4 | 4 | V | 2 | ||
| VREF sourcing current | 0 | 1 | mA | 2 | |||
| VS input voltage range | VS | 3 | 5.5 | V | 2 | ||
| VINP, VINM input voltage range | VINP, VINM | 0 | 24 | V | 2 | ||
| Operating free air temperature | Tstg | -40 | 85 | °C | 2 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 2 | ||
| Input voltage range VCC, Sense, Enable, OUT | -0.3 | 100 | V | 3 | |||
| Supply voltage VS | VS | -0.3 | 6 | V | GND - 0.3 to 6 | 3 | |
| Input voltage common mode VINP, VINM | -0.3 | 26 | V | common mode | 3 | ||
| Input voltage differential VINP, VINM | -26 | 26 | V | differential | 3 | ||
| Input voltage range PROG | PROG | -0.3 | 6 | V | 3 | ||
| Output voltage range GATE, PG | -0.3 | 100 | V | 3 | |||
| Output voltage range TIMER, VREF | -0.3 | 6 | V | 3 | |||
| Sink current PG | 10 | mA | 3 | ||||
| Source current VREF | 0 | 2 | mA | 3 | |||
| Sink current PROG | PROG | 2 | mA | 3 | |||
| SDA voltage | SDA | -0.3 | 6 | V | GND - 0.3 to + 6.0 | 3 | |
| Current into SDA, SCL, VS, VINP, VINM, A0, A1, GNDB | 5 | mA | 3 | ||||
| Open drain digital output current | 10 | mA | 3 | ||||
| ESD rating HBM | 2 | kV | HBM | 3 | |||
| ESD rating CDM | 500 | V | CDM | 3 | |||
| Operating junction temperature range | TJ | -40 | 125 | °C | 3 | ||
| Storage temperature range | Tstg | -40 | 150 | °C | 3 | ||
| Junction-to-ambient thermal resistance (low-k) | qJA | 88.3 | °C/W | 2 | |||
| Junction-to-ambient thermal resistance (high-k) | qJA | 74.5 | °C/W | 2 | |||
| Supply current enabled | IVCC | 450 | 1000 | mA | VEN = Hi VSENSE = VOUT = VVCC | 4 | |
| Supply current disabled | IVCC | 90 | 250 | mA | VEN = Lo VSENSE = VVCC = VOUT = 0 | 4 | |
| Quiescent current operating | IVS | 0.7 | 1 | mA | 4 | ||
| Quiescent current power down mode | IVS | 6 | 15 | mA | Power down mode | 4 | |
| Input bias current (SENSE) | ISENSE | 7.5 | 20 | mA | VSENSE = VVCC VOUT = VVCC | 4 | |
| Reference voltage | VREF | 3.9 | 4 | 4.1 | V | 0 < IVREF < 1 mA | 4 |
| Pulldown resistance device disabled | RPROG | 375 | 600 | Ω | IPROG = 200 mA; VEN = 0 V | 4 | |
| Current sense threshold with power limiting trip | VCL | 17 | 25 | 33 | mV | VPROG = 2.4 V; VOUT = 0 V or VPROG = 0.9 V; VOUT = 30 V; VVCC = 48 V | 4 |
| Current sense threshold without power limiting trip | VSENSE | 45 | 50 | 55 | mV | VPROG = 4 V; VSENSE = VOUT | 4 |
| Charge current sourcing | ISOURCE | 15 | 25 | 34 | mA | VTIMER = 0 V | 4 |
| Charge current sourcing TJ = 25°C | ISOURCE | 20 | 25 | 30 | mA | VTIMER = 0 V; TJ = 25°C | 4 |
| Discharge current sinking | ISINK | 1.5 | 2.5 | 3.7 | mA | VTIMER = 5 V | 4 |
| Discharge current sinking TJ = 25°C | ISINK | 2.1 | 2.5 | 3.1 | mA | VTIMER = 5 V; TJ = 25°C | 4 |
| TIMER upper threshold voltage | 3.9 | 4 | 4.1 | V | 4 | ||
| GATE sourcing current | IGATE | 15 | 22 | 35 | mA | VSENSE = VVCC; V(GATE-OUT) = 7 V; VEN = Hi | 4 |
| GATE sinking current EN low | 1.8 | 2.4 | 2.8 | mA | VEN = Lo; VGATE = VVCC | 4 | |
| GATE sinking current EN high | 75 | 125 | 250 | mA | VEN = Hi; VGATE = VVCC; V(VCC-SENSE) 200 mV | 4 | |
| GATE output voltage | VGATE-OUT | 12 | 16 | V | 4 | ||
| Power good low voltage IPG = 2 mA | VPG_L | 0.1 | 0.25 | V | IPG = 2 mA | 5 | |
| Power good low voltage IPG = 4 mA | VPG_L | 0.25 | 0.5 | V | IPG = 4 mA | 5 | |
| PG threshold voltage rising (PG goes open drain) | VPGTL | 0.8 | 1.25 | 1.7 | V | VSENSE = VVCC; measure V(VCC-OUT) rising; PG goes open drain | 5 |
| PG threshold voltage falling (PG goes low) | VPGTH | 2.2 | 2.7 | 3.2 | V | VSENSE = VVCC; measure V(VCC-OUT) falling; PG goes low | 5 |
| PG deglitch delay | tDPG | 5 | 9 | 15 | ms | VSENSE = VVCC | 5 |
| Enable threshold going high | VEN_H | 1.32 | 1.35 | 1.38 | V | VEN going high | 5 |
| Enable threshold going low | VEN_L | 1.2 | 1.25 | 1.3 | V | VEN going low | 5 |
| VVCC turn on voltage | VVCC | 8.4 | 8.8 | V | Rising | 5 | |
| VVCC turn off voltage | VVCC | 7.2 | 8.3 | V | Falling | 5 | |
| Digital input leakage current | ILEAKAGE | 0.1 | 1 | mA | 0 < VIN < VS | 5 | |
| SDA low output voltage | VLO | 0.15 | 0.4 | V | SDA low output sinking 5 mA | 5 | |
| SDA high level leakage current | ILEAKAGE | 0.1 | 1 | mA | VOUT = VS | 5 | |
| CSA gain error | GainCSA | -0.04 | 0.04 | % | 6 | ||
| Current measurement error | -1 | 1 | % | Over full range | 6 | ||
| Bus voltage input range BRNG = 1 | 0 | 32 | V | BRNG = 1 | 6 | ||
| Bus voltage input range BRNG = 0 | 0 | 16 | V | BRNG = 0 | 6 |
CAD (KiCad official)
- Symbol:
TPS2480PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
tps2480pw-etched.step/tps2480pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2480pw.step/tps2480pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (60 pp, sha256
b6a2a9a5f88be0ad, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TPS2480PW
**Texas Instruments** · Supervisor And Reset ICs · TSSOP-20
TPS2480PW from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDA | bidirectional | I2C data line for the TPS2480/81 interface, with data input from the I2C bus. |
| 2 | SCL | input | I2C clock input for the TPS2480/81 interface. |
| 3 | NC | unconnected | No internal connection; tie to GND or float. |
| 4 | VS | power_in | Power input to the I2C block, 3.3 V to 5 V, used as the power source for the logic and I2C interface. |
| 5 | NC | unconnected | No connection; tie to GND or float. |
| 6 | EN | input | Device enable input; the GATE driver is enabled only when the positive threshold is exceeded and the internal POR and UVLO thresholds are satisfied. |
| 7 | VREF | power_in | Reference voltage output of 4.0 V used with a resistor divider to set the PROG pin voltage; no more than 1 mA may be drawn. |
| 8 | PROG | input | Power-limit setting input; the applied voltage must stay within 0.4 V to 4.0 V and must not exceed 4 V. |
| 9 | TIMER | passive | Fault timing capacitor pin; the timer charges at 25 mA and discharges at 2.5 mA, and the pin should be tied to ground if the feature is not used. |
| 10 | GND | power_in | System ground. |
| 11 | PG | output | Open-drain power good output that goes high-impedance after the external FET VDS falls to about 1.25 V and a 9-ms deglitch period has elapsed. |
| 12 | OUT | input | Output voltage feedback input used to measure the external FET VDS as V(SENSE-OUT). |
| 13 | GATE | output | High-side gate drive output for the external N-channel FET, with a 22 mA pull-up and a 75 mA (min) pull-down. |
| 14 | SENSE | input | Current-limit sense input monitoring the drain of the external FET and RS; it is internally clamped to VCC, so it must not be driven to a large voltage difference from VCC. |
| 15 | VCC | power_in | Main power supply input to the device and FET; it must exceed the POR (about 6 V) and UVLO (about 8 V) thresholds before normal operation. |
| 16 | GND | power_in | System ground. |
| 17 | VINP | input | Positive differential shunt voltage input, Kelvin connected to the positive side of the current sensing resistor. |
| 18 | VINM | input | Negative differential shunt voltage input, Kelvin connected to the negative side of the current sensing resistor; bus voltage is measured from this pin to GND. |
| 19 | A1 | input | Address pin for setting the I2C address, tied to GND, SDA, SCL or VS as shown in Table 2. |
| 20 | A0 | input | Address pin for setting the I2C address, tied to GND, SDA, SCL or VS as shown in Table 2. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC input voltage range | VCC | 9 | | 80 | V | | 2 |
| PROG input voltage range | PROG | 0.4 | | 4 | V | | 2 |
| VREF sourcing current | | 0 | | 1 | mA | | 2 |
| VS input voltage range | VS | 3 | | 5.5 | V | | 2 |
| VINP, VINM input voltage range | VINP, VINM | 0 | | 24 | V | | 2 |
| Operating free air temperature | Tstg | -40 | | 85 | °C | | 2 |
| Operating junction temperature | TJ | -40 | | 125 | °C | | 2 |
| Input voltage range VCC, Sense, Enable, OUT | | -0.3 | | 100 | V | | 3 |
| Supply voltage VS | VS | -0.3 | | 6 | V | GND - 0.3 to 6 | 3 |
| Input voltage common mode VINP, VINM | | -0.3 | | 26 | V | common mode | 3 |
| Input voltage differential VINP, VINM | | -26 | | 26 | V | differential | 3 |
| Input voltage range PROG | PROG | -0.3 | | 6 | V | | 3 |
| Output voltage range GATE, PG | | -0.3 | | 100 | V | | 3 |
| Output voltage range TIMER, VREF | | -0.3 | | 6 | V | | 3 |
| Sink current PG | | | | 10 | mA | | 3 |
| Source current VREF | | 0 | | 2 | mA | | 3 |
| Sink current PROG | PROG | | | 2 | mA | | 3 |
| SDA voltage | SDA | -0.3 | | 6 | V | GND - 0.3 to + 6.0 | 3 |
| Current into SDA, SCL, VS, VINP, VINM, A0, A1, GNDB | | | | 5 | mA | | 3 |
| Open drain digital output current | | | | 10 | mA | | 3 |
| ESD rating HBM | | | | 2 | kV | HBM | 3 |
| ESD rating CDM | | | | 500 | V | CDM | 3 |
| Operating junction temperature range | TJ | -40 | | 125 | °C | | 3 |
| Storage temperature range | Tstg | -40 | | 150 | °C | | 3 |
| Junction-to-ambient thermal resistance (low-k) | qJA | | 88.3 | | °C/W | | 2 |
| Junction-to-ambient thermal resistance (high-k) | qJA | | 74.5 | | °C/W | | 2 |
| Supply current enabled | IVCC | | 450 | 1000 | mA | VEN = Hi VSENSE = VOUT = VVCC | 4 |
| Supply current disabled | IVCC | | 90 | 250 | mA | VEN = Lo VSENSE = VVCC = VOUT = 0 | 4 |
| Quiescent current operating | IVS | | 0.7 | 1 | mA | | 4 |
| Quiescent current power down mode | IVS | | 6 | 15 | mA | Power down mode | 4 |
| Input bias current (SENSE) | ISENSE | | 7.5 | 20 | mA | VSENSE = VVCC VOUT = VVCC | 4 |
| Reference voltage | VREF | 3.9 | 4 | 4.1 | V | 0 < IVREF < 1 mA | 4 |
| Pulldown resistance device disabled | RPROG | | 375 | 600 | Ω | IPROG = 200 mA; VEN = 0 V | 4 |
| Current sense threshold with power limiting trip | VCL | 17 | 25 | 33 | mV | VPROG = 2.4 V; VOUT = 0 V or VPROG = 0.9 V; VOUT = 30 V; VVCC = 48 V | 4 |
| Current sense threshold without power limiting trip | VSENSE | 45 | 50 | 55 | mV | VPROG = 4 V; VSENSE = VOUT | 4 |
| Charge current sourcing | ISOURCE | 15 | 25 | 34 | mA | VTIMER = 0 V | 4 |
| Charge current sourcing TJ = 25°C | ISOURCE | 20 | 25 | 30 | mA | VTIMER = 0 V; TJ = 25°C | 4 |
| Discharge current sinking | ISINK | 1.5 | 2.5 | 3.7 | mA | VTIMER = 5 V | 4 |
| Discharge current sinking TJ = 25°C | ISINK | 2.1 | 2.5 | 3.1 | mA | VTIMER = 5 V; TJ = 25°C | 4 |
| TIMER upper threshold voltage | | 3.9 | 4 | 4.1 | V | | 4 |
| GATE sourcing current | IGATE | 15 | 22 | 35 | mA | VSENSE = VVCC; V(GATE-OUT) = 7 V; VEN = Hi | 4 |
| GATE sinking current EN low | | 1.8 | 2.4 | 2.8 | mA | VEN = Lo; VGATE = VVCC | 4 |
| GATE sinking current EN high | | 75 | 125 | 250 | mA | VEN = Hi; VGATE = VVCC; V(VCC-SENSE) 200 mV | 4 |
| GATE output voltage | VGATE-OUT | 12 | | 16 | V | | 4 |
| Power good low voltage IPG = 2 mA | VPG_L | | 0.1 | 0.25 | V | IPG = 2 mA | 5 |
| Power good low voltage IPG = 4 mA | VPG_L | | 0.25 | 0.5 | V | IPG = 4 mA | 5 |
| PG threshold voltage rising (PG goes open drain) | VPGTL | 0.8 | 1.25 | 1.7 | V | VSENSE = VVCC; measure V(VCC-OUT) rising; PG goes open drain | 5 |
| PG threshold voltage falling (PG goes low) | VPGTH | 2.2 | 2.7 | 3.2 | V | VSENSE = VVCC; measure V(VCC-OUT) falling; PG goes low | 5 |
| PG deglitch delay | tDPG | 5 | 9 | 15 | ms | VSENSE = VVCC | 5 |
| Enable threshold going high | VEN_H | 1.32 | 1.35 | 1.38 | V | VEN going high | 5 |
| Enable threshold going low | VEN_L | 1.2 | 1.25 | 1.3 | V | VEN going low | 5 |
| VVCC turn on voltage | VVCC | | 8.4 | 8.8 | V | Rising | 5 |
| VVCC turn off voltage | VVCC | | 7.2 | 8.3 | V | Falling | 5 |
| Digital input leakage current | ILEAKAGE | | 0.1 | 1 | mA | 0 < VIN < VS | 5 |
| SDA low output voltage | VLO | | 0.15 | 0.4 | V | SDA low output sinking 5 mA | 5 |
| SDA high level leakage current | ILEAKAGE | | 0.1 | 1 | mA | VOUT = VS | 5 |
| CSA gain error | GainCSA | -0.04 | | 0.04 | % | | 6 |
| Current measurement error | | -1 | | 1 | % | Over full range | 6 |
| Bus voltage input range BRNG = 1 | | 0 | | 32 | V | BRNG = 1 | 6 |
| Bus voltage input range BRNG = 0 | | 0 | | 16 | V | BRNG = 0 | 6 |
## CAD (KiCad official)
- Symbol: `TPS2480PW`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `tps2480pw-etched.step` / `tps2480pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tps2480pw.step` / `tps2480pw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tps2480.pdf) (60 pp, sha256 `b6a2a9a5f88be0ad`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tps2480pw-datasheet.pdf)