TPS2456ARHHR from Texas Instruments, in a VQFN-36-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SENPA	input	Input voltage sense for channel A, connected to the source side of RSENSEA; used for fast trip, UVLO (trips when SENPA is below 8.5 V for more than 440 ns nominal) and blocking.
2	SETA	input	Connect RSETA from the input supply to SETA to program the channel A current limit together with RSENSEA and RMONA.
3	SENMA	input	Connect to the load side of RSENSEA; the fast-trip threshold equals 100 mV / RSENSEA.
4	VINT	bidirectional	Internal bias rail (about 2.35 V) that requires a bypass capacitor to GND and is not designed as a general-purpose bias rail.
5	MONA	bidirectional	Connect RMONA from MONA to GND to set the channel A current limit together with RSENSEA and RSETA; the current limit acts at VMONA = 675 mV.
6	ORENA	input	Active-high blocking transistor enable; pulling it low disables blocking by holding GAT2A low, and an internal 200 kΩ resistor pulls it to VINT.
7	GND	power_in	Connect pin to ground.
8	GND	power_in	Connect pin to ground.
9	MONB	bidirectional	Connect RMONB from MONB to GND to set the channel B current limit together with RSENSEB and RSETB; the current limit acts at VMONB = 675 mV.
10	CTB	bidirectional	Connect a capacitor from CTB to GND to set the fault timer period; the channel shuts down and declares a fault when VCTB reaches 1.35 V.
11	GAT2B	output	Gate drive for the channel B blocking MOSFET; sources 30 µA to turn the MOSFET on and is clamped no more than 14.5 V above OUTB.
12	OUTB	bidirectional	Output voltage monitor and bias input for channel B, used by the biasing, blocking and power-good circuits.
13	GND	power_in	Connect pin to ground.
14	ORENB	input	Active-high blocking transistor enable; pulling it low disables blocking by holding GAT2B low, and an internal 200 kΩ resistor pulls it to VINT.
15	GAT1B	output	Gate drive for the channel B protection MOSFET; sources 30 µA to turn the MOSFET on and is clamped no more than 14.5 V above INB.
16	SENMB	input	Connect to the load side of RSENSEB; the fast-trip threshold equals 100 mV / RSENSEB.
17	SETB	input	Connect RSETB from the input supply to SETB to program the channel B current limit together with RSENSEB and RMONB.
18	SENPB	input	Input voltage sense for channel B, connected to the source side of RSENSEB; used for fast trip, UVLO (trips when SENPB is below 8.5 V for more than 440 ns nominal) and blocking.
19	INB	power_in	Control power input for channel B, connected to the input supply; recommended VINx range is 8.5 V to 15 V.
20	NC	unconnected	No connection.
21	FLTB	output	Active-low open-drain fault output for channel B, asserted when the B fault timer runs out; may be left open if not used.
22	PGB	output	Active-low open-drain power-good output for channel B, asserting when VOUTB exceeds 10.63 V and releasing below 10.50 V.
23	GND	power_in	Connect pin to ground.
24	GND	power_in	Connect pin to ground.
25	GND	power_in	Connect pin to ground.
26	PGA	output	Active-low open-drain power-good output for channel A, asserting when VOUTA exceeds 10.63 V and releasing below 10.50 V.
27	FLTA	output	Active-low open-drain fault output for channel A, asserted when the A fault timer runs out; may be left open if not used.
28	GND	power_in	Connect pin to ground.
29	ENB	input	Active-high enable for channel B; a low level turns the channel off by pulling GAT1B and GAT2B low, and an internal 200 kΩ resistor pulls it to VINT.
30	GAT1A	output	Gate drive for the channel A protection MOSFET; sources 30 µA to turn the MOSFET on and is clamped no more than 14.5 V above INA.
31	ENA	input	Active-high enable for channel A; a low level turns the channel off by pulling GAT1A and GAT2A low, and an internal 200 kΩ resistor pulls it to VINT.
32	GND	power_in	Connect pin to ground.
33	OUTA	bidirectional	Output voltage monitor and bias input for channel A, used by the biasing, blocking and power-good circuits.
34	GAT2A	output	Gate drive for the channel A blocking MOSFET; sources 30 µA to turn the MOSFET on and is clamped no more than 14.5 V above OUTA.
35	CTA	bidirectional	Connect a capacitor from CTA to GND to set the fault timer period; the channel shuts down and declares a fault when VCTA reaches 1.35 V.
36	INA	power_in	Control power input for channel A, connected to the input supply; recommended VINx range is 8.5 V to 15 V.
37	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-36-EP(6x6)
Category	Power Management ICs
Pins	37

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
GAT1x, GAT2x voltage		-0.3		30	V		2
INx, OUTx, SENPx, SENMx, SETx, ENx, FLTx, PGx, ORENx voltage		-0.3		20	V		2
CTx, MONx voltage		-0.3		5	V		2
FLTx, PGx current sinking				5	mA		2
MONx current sourcing				5	mA		2
VINT current		-1		1	mA		2
ESD Human Body Model				2	kV	Human Body Model	2
ESD Charged Device Model				0.5	kV	Charged Device Model	2
VINx input voltage	VINx	8.5	12	15	V		3
IMONx	IMONx	100		1000	µA		3
GAT1x, GAT2x board leakage current		-1		1	µA	PCB condition; footnote: not a limit on the TPS2456A	3
VINT bypass capacitance	VINT	1	100	250	nF		3
Operating junction temperature range	TJ	-40		125	°C		3
Threshold voltage VINx ↑ (Enable input ENx, ORENx)		1.25	1.35	1.45	V		3
Hysteresis (Enable input ENx, ORENx)		20	50	80	mV		3
Pullup current (ENx, ORENx)		5	8	15	µA	ENx = ORENx = 0 V, current sourcing	3
Input bias current (ENx, ORENx)			6	15	µA	ENx = ORENx = 17 V, current sinking	3
Turn off time				20	µs	ENx deasserts to VOUTx < 1 V, COUT = 0 µF, QGAT1x = 33 nF	3
Output low voltage (PGx)			0.14	0.25	V	IPGx = 2 mA sinking	3
Leakage current (PGx)				1	µA	PGx = 17 V (sinking)	3
Threshold voltage PGx, VOUTx ↓		10.2	10.5	10.8	V		3
Deglitch time (PGx)		50	100	150	µs	PGx falling	3
Output low voltage (FLTx)			0.14	0.25	V	IFLTx = 2 mA sinking	3
Leakage current (FLTx)				1	µA	VFLTx = 17 V (sinking)	3
Output voltage (VINT bias supply)	VINT	2	2.3	2.8	V	0 < IVINT < 50 µA	3
Sourcing current (CTx)		7	10	13	µA	VCTx = 0 V, during fault	3
Upper threshold voltage (CTx)		1.3	1.35	1.4	V		3
Timer start threshold		5	6	7	V	(VGAT1x, VINx) when timer starts, with VGAT1x falling due to over current	3
Input referred offset (MONx)		-1.5		1.5	mV	10.8 V ≤ VSENMx ≤ 13.2 V, VSENPx = VSENMx + 50 mV, measure VSETx, VSENMx	3
MONx threshold		0.66	0.675	0.69	V	VGAT1x = 15 V	3
Leakage current (MONx)				1	µA	VSETx = (VSENMx, 10 mV)	3
Current limit threshold		47.5	50	52.5	mV	RSETx = 500 Ω, RMONx = 6800 Ω, measure VSENPx, VSENMx when VGAT1x = 15 V	4
Sink current in current limit			20	40	µA	VMONx = 1 V, VGAT1x = 12 V, measure IGAT1x	4
Fast trip threshold		80	100	120	mV	Measure VSENPx, VSENMx	4
Fast turn-off delay			200	300	ns	(VSENP, VSENM): 0 V → 120 mV, tP50-50	4
UVLO SENPx rising		8.1	8.5	8.9	V		4
UVLO hysteresis SENPx falling		0.44	0.5	0.59	V		4
Blocking comparator turn-on threshold		5	10	20	mV	Measure (VSENPx, VOUTx)	4
Blocking comparator turn-off threshold		-6	-3	0	mV	Measure (VSENPx, VOUTx)	4
Blocking comparator turn-off delay			200	300	ns	20 mV overdrive, tp50-50	4
Gate driver output voltage (GAT1x, GAT2x)		21.5	23	24.5	V	VINx = VOUTx = 10 V	4
Gate driver sourcing current (GAT1x, GAT2x)		20	30	40	µA	VINx = VOUTx = 10 V, VGAT1x = VGAT2x = 17 V	4
Fast turnoff sinking current (GAT1x, GAT2x)			0.5	1	A	VGAT1x = VGAT2x = 14 V, pulsed measurement	4
Sustained sinking current (GAT1x, GAT2x)		6	14	20	mA	4 V ≤ (VGAT1x = VGAT2x) ≤ 25 V	4
Pulldown resistance (GAT1x, GAT2x)		14	20	26	kΩ	In thermal shutdown	4
Fast turn-off duration		5	10	15	µs		4
Disable delay (ENx to VGAT1x and VGAT2x)				1	µs	ENx pin to VGATx1 and VGAT2x, tP50-90	4
Startup time (ENx and ORENx high)				0.25	ms	INx rising to GAT1x or GAT2x sourcing current	4
Supply current, both channels enabled			3.1	4	mA	Both channels enabled	4
Supply current, both channels disabled			2	2.8	mA	Both channels disabled	4
Thermal shutdown temperature, rising	TJ		140	150	°C	rising	4
Discharge pulldown (CTx)			200		Ω		3
Blocking hysteresis PGx, VOUTx ↑			130		mV	PGx, VOUTx ↑	3
Thermal shutdown hysteresis			10		°C		4
Junction-to-ambient thermal resistance	θJA		32		°C/W		2
Junction-to-case (top) thermal resistance	θJC(top)		23		°C/W		2
Junction-to-board thermal resistance	θJB		11		°C/W		2
Junction-to-case (bottom) thermal resistance	θJC(bottom)		2.1		°C/W		2

CAD (KiCad official)

Symbol: TPS2456ARHHR
Footprint: Package_DFN_QFN:QFN-36-1EP_6x6mm_P0.5mm_EP3.7x3.7mm
3D model: VQFN-36-EP(6x6) (KiCad packages3D, STEP)
3D model files: tps2456arhhr-etched.step / tps2456arhhr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2456arhhr.step / tps2456arhhr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (32 pp, sha256 d647865d5e23c5c8, retrieved 2026-10-31, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS2456ARHHR

Verified TPS2456ARHHR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README