TPS2419PWR from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RSET	input	A resistor from this pin to GND programs the V(A-C) turn-off threshold, and leaving it open gives a slightly positive turn-off threshold.
2	EN	input	EN must be pulled above 1.3 V to permit normal ORing operation, a low on EN holds GATE low, and it should not be driven above its recommended maximum voltage of 5 V.
3	RSVD	power_in	This reserved pin must be connected to GND.
4	GND	power_in	Device ground, which should have a low-impedance connection to the ground plane because it carries several amperes of discharge current when the external MOSFET turns off.
5	GATE	output	This pin drives the gate of the external N-channel MOSFET to emulate a low forward-voltage diode, with an absolute maximum GATE/BYP voltage of -0.3 V to 30 V.
6	C	input	This is the cathode voltage sense input and the bias supply for the gate-drive charge pump, which must be at 3 V or greater for the MOSFET to turn on and has an absolute maximum rating of 18 V.
7	A	input	This is the simulated diode anode voltage sense input and the reference for the BYP charge-pump supply, connected to the MOSFET source in the typical configuration, with an absolute maximum rating of -0.3 V to 18 V.
8	BYP	bidirectional	A capacitor from BYP to A (2200 pF ceramic recommended) filters the internal charge-pump supply, and shorting this pin to a voltage below A damages the device, with an absolute maximum of -0.3 V to 13 V to A.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-8
Category	Power Management ICs
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
A, C input voltage range		0		16.5	V	Voltages referenced to GND	3
EN input voltage range		0		5	V		3
R(RSET) resistance range	R(RSET)	1.5			kΩ	Printed as 1.5 to ∞	3
TJ operating junction temperature	TJ	-40		125	°C		3
A to C operational voltage			5		V		3
Supply UVLO, V(C) rising		2.25		2.5	V	V(C) rising	3
Supply UVLO hysteresis			0.25		V		3
/I(A)/ gate in active region	I(A)		0.66	1	mA	Gate in active region	3
/I(A)/ gate saturated high	I(A)		0.1		mA	Gate saturated high	3
C current, worst case, gate in active region	I(C)	4.25		6	mA	Worst case, gate in active region, V(AC) ≤ 0.1 V	3
C current, gate saturated high	I(C)		1.2		mA	Gate saturated high, V(AC) ≤ 0.1 V	3
EN threshold voltage, rising	V(EN)	1.25	1.3	1.35	V	V(EN) rising	3
EN hysteresis			29		mV		3
EN response time, enable (rising)		0.65		1	µs	V(AC) = 0.1 V, V(EN)↑: 1.1 V → 1.4 V, measure period to V(GATE) = 0.25 V	3
EN response time, disable (falling)		0.3		0.6	µs	V(AC) = 0.1 V, V(EN)↓: 1.4 V → 1.1 V, measure period to V(GATE) = V(ON) - 0.25 V	3
EN leakage current (source or sink)				1	µA	V(EN) = 0.5 V	3
Forward turn-on voltage	VON	58	65	71	mV	V(A-C)	3
Turn-off threshold voltage, R(RSET) open	V(A-C)	1	3	5	mV	Gate sinks > 10 mA at V(GATE-A) = 2 V; V(A-C) falling, R(RSET) = open	3
Turn-off threshold voltage, R(RSET) = 28.7 kΩ	V(A-C)	-17	-13.25	-10	mV	Gate sinks > 10 mA at V(GATE-A) = 2 V; V(A-C) falling, R(RSET) = 28.7 kΩ	3
Turn-off threshold voltage, R(RSET) = 3.24 kΩ	V(A-C)	-170	-142	-114	mV	Gate sinks > 10 mA at V(GATE-A) = 2 V; V(A-C) falling, R(RSET) = 3.24 kΩ	3
Turn-off delay			70		ns	V(A) = 12 V, V(A-C): 20 mV → -20 mV; measured until V(GATE-A) begins to decrease	3
Turn-off time			130		ns	V(A) = 12 V, C(GATE-GND) = 0.01 µF, V(A-C): 20 mV → -20 mV, measure period to V(GATE) = V(A)	3
Gate positive drive voltage, V(C) = 3 V	V(GATE-A)	6	7	8	V	V(C) = 3 V, V(A-C) = 200 mV	4
Gate positive drive voltage, 5 V ≤ VC ≤ 18 V	V(GATE-A)	9	10.2	11.5	V	5 V ≤ VC ≤ 18 V, V(A-C) = 200 mV	4
Gate source current		250	290	350	µA	V(A-C) = 200 mV, V(GATE-A) = 4 V	4
Turn-off pulsed current, V(GATE) = 8 V	I(GATE)	1.75		2.35	A	V(A-C) = -0.1 V, V(GATE) = 8 V	4
Turn-off pulsed current, V(GATE) = 5 V	I(GATE)	1.25		1.75	A	V(A-C) = -0.1 V, V(GATE) = 5 V	4
Turn-off pulsed current period		7.5		12.5	µs		4
Sustain turn-off current, I(GATE)	I(GATE)	15		19.5	mA	V(A-C) = -0.1 V, 3 V ≤ VC ≤ 18 V, 2 V ≤ V(GATE) ≤ 18 V	4
Thermal shutdown temperature			135		°C	Temperature rising, TJ	4
Thermal hysteresis			10		°C		4
A, C voltage		-0.3		18	V	Voltages referenced to GND	2
A above C voltage				7.5	V		2
C above A voltage				18	V		2
GATE, BYP voltage		-0.3		30	V		2
BYP to A voltage		-0.3		13	V		2
GATE above BYP voltage				0.3	V		2
RSET voltage		-0.3		7	V		2
EN voltage		-0.3		5.5	V		2
ESD human body model				2	kV	Human body model	2
ESD charged device model				500	V	Charged device model	2
Thermal resistance junction-to-ambient, PW (TSSOP), low-k	θJA		258		°C/W	PW (TSSOP) package, low-k board	2
Thermal resistance junction-to-ambient, PW (TSSOP), high-k	θJA		159		°C/W	PW (TSSOP) package, high-k board	2

CAD (KiCad official)

Symbol: TPS2419PWR
Footprint: Package_SO:TSSOP-8_4.4x3mm_P0.65mm
3D model: TSSOP-8 (KiCad packages3D, STEP)
3D model files: tps2419pwr-etched.step / tps2419pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2419pwr.step / tps2419pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (29 pp, sha256 5d2098bd9b468e95, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

TPS2419PWR

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3D Model

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