component

TPS2388RTQR

Public Made by Adom

by adom

Texas Instruments Ethernet ICs, QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232tps2388rtqrfactory-2.0.0extractor-text

Verified TPS2388RTQR

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 57 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TPS2388RTQR · QFN-56-EP(8x8) · 57 pins
  • ✓copper: 57 copper pads, none touching another net
  • ✓datasheet: all 57 pin names found in the 87-page datasheet
  • ✓distributor: lcsc C544512, digikey 296-TPS2388RTQRTR-ND, mouser 595-TPS2388RTQR
  • ✓family: QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ra9pxb5k/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.76)
  • ✓pads: 57 pins = 57 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 57 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tps2388rtqr.kicad_sym✓ tps2388rtqr.kicad_mod✓ tps2388rtqr.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers tps2388rtqr: viewers · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
tps2388rtqr-etched.glb Publish 0.1.0 · Ray 1d ago
tps2388rtqr-etched.step tps2388rtqr: factory component page (tier=mfr) · Ray 1d ago
tps2388rtqr-hero.glb tps2388rtqr: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
tps2388rtqr-hero.overlay.json Publish 0.1.0 · Ray 1d ago
tps2388rtqr.glb Publish 0.1.0 · Ray 1d ago
tps2388rtqr.kicad_mod Publish 0.1.0 · Ray 1d ago
tps2388rtqr.kicad_sym Publish 0.1.0 · Ray 1d ago
tps2388rtqr.lbr Publish 0.1.0 · Ray 1d ago
tps2388rtqr.step Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier mfr, 57 pins · Ray 1d ago

TPS2388RTQR

Texas Instruments · Ethernet ICs · QFN-56-EP(8x8)

TPS2388RTQR from Texas Instruments, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GAT1 output Port 1 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
2 SEN1 input Port 1 current sense input, measured differentially against KSENSA; tie to AGND if the port is not used.
3 DRAIN1 input Port 1 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
4 KSENSA input Kelvin point connection for the differential current-sense measurement of SEN1 and SEN2.
5 DRAIN2 input Port 2 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
6 SEN2 input Port 2 current sense input, measured differentially against KSENSA; tie to AGND if the port is not used.
7 GAT2 output Port 2 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
8 GAT3 output Port 3 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
9 SEN3 input Port 3 current sense input, measured differentially against KSENSB; tie to AGND if the port is not used.
10 DRAIN3 input Port 3 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
11 KSENSB input Kelvin point connection for the differential current-sense measurement of SEN3 and SEN4.
12 DRAIN4 input Port 4 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
13 SEN4 input Port 4 current sense input, measured differentially against KSENSB; tie to AGND if the port is not used.
14 GAT4 output Port 4 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
15 NC unconnected No-connect pin, internally biased at 1/3 and 2/3 of VPWR to control the voltage gradient from VPWR; leave open.
16 NC unconnected No-connect pin, internally biased at 1/3 and 2/3 of VPWR to control the voltage gradient from VPWR; leave open.
17 VPWR power_in Analog 48-V positive supply, nominally 48 V with a recommended range of 44 V to 57 V; bypass with 0.1 µF to the AGND pin.
18 NC unconnected No-connect pin, internally biased at 1/3 and 2/3 of VPWR to control the voltage gradient from VPWR; leave open.
19 NC unconnected No-connect pin, internally biased at 1/3 and 2/3 of VPWR to control the voltage gradient from VPWR; leave open.
20 ATST_DCPL0 output Used for internal test purposes only; no bypass capacitor is needed.
21 AGND power_in Analog ground; connect to the GND plane and the exposed thermal pad.
22 NC unconnected No-connect pin; leave open.
23 TEST0 bidirectional Used internally for test purposes only; leave open.
24 TEST1 bidirectional Used internally for test purposes only; leave open.
25 TEST2 bidirectional Used internally for test purposes only; leave open.
26 TEST3 bidirectional Used internally for test purposes only; leave open.
27 Resv unconnected Reserved no-connect pin; leave open.
28 Resv unconnected Reserved no-connect pin; leave open.
29 GAT5 output Port 5 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
30 SEN5 input Port 5 current sense input, measured differentially against KSENSC; tie to AGND if the port is not used.
31 DRAIN5 input Port 5 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
32 KSENSC input Kelvin point connection for the differential current-sense measurement of SEN5 and SEN6.
33 DRAIN6 input Port 6 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
34 SEN6 input Port 6 current sense input, measured differentially against KSENSC; tie to AGND if the port is not used.
35 GAT6 output Port 6 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
36 GAT7 output Port 7 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
37 SEN7 input Port 7 current sense input, measured differentially against KSENSD; tie to AGND if the port is not used.
38 DRAIN7 input Port 7 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
39 KSENSD input Kelvin point connection for the differential current-sense measurement of SEN7 and SEN8.
40 DRAIN8 input Port 8 output voltage monitor and detect sense, with an internal resistor to VPWR except during detection or while the port is ON; leave floating or tie to AGND if unused.
41 SEN8 input Port 8 current sense input, measured differentially against KSENSD; tie to AGND if the port is not used.
42 GAT8 output Port 8 gate drive output for the external N-channel MOSFET, pulled low when any input supply is low or an overcurrent timeout occurs; leave floating if unused.
43 VDD power_in Digital 3.3-V supply (recommended 3.0 V to 3.6 V); bypass with 0.1 µF to the DGND pin.
44 RESET input Active-low reset input that resets the TPS2388 when asserted low; internally pulled up to VDD with a 1-µs to 5-µs deglitch filter.
45 INT output Open-drain interrupt output that asserts low when a bit in the interrupt register is asserted.
46 DGND power_in Digital ground; connect to the GND plane and the exposed thermal pad.
47 DTST_DCPL1 output Used for internal test purposes only; no bypass capacitor is needed.
48 A1 input I2C address input A1, internally pulled up to VDD.
49 A2 input I2C address input A2, internally pulled up to VDD.
50 A3 input I2C address input A3, internally pulled up to VDD.
51 A4 input I2C address input A4, internally pulled up to VDD.
52 Resv unconnected Reserved no-connect pin; leave open.
53 SCL input Serial clock input for the I2C bus.
54 SDAI input Serial data input for the I2C bus; can be connected to SDAO for non-isolated systems.
55 SDAO output Open-drain serial data output for the I2C bus that requires an external pull-up; can be connected to SDAI for non-isolated systems.
56 OSS input Active-high port 1-8 fast shutdown input with an internal 1-µs to 5-µs deglitch filter, internally pulled down to DGND.
57 Thermal pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-56-EP(8x8)
Category Communication Interface Chip/UART/485/232
Pins 57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage VVDD 3 3.3 3.6 V Over operating free-air temperature range 6
VPWR supply voltage VVPWR 44 48 57 V Over operating free-air temperature range 6
Voltage slew rate on VPWR 1 V/µs Over operating free-air temperature range 6
Operating junction temperature TJ -40 125 °C Over operating free-air temperature range 6
Operating free-air temperature TA -40 85 °C Over operating free-air temperature range 6
Input voltage VPWR -0.3 70 V Over operating free-air temperature range (unless otherwise noted) 6
Input voltage VDD -0.3 4 V Over operating free-air temperature range (unless otherwise noted) 6
Input voltage OSS, RESET, A1-A4 -0.3 4 V Over operating free-air temperature range (unless otherwise noted) 6
Input voltage SEN1-8, KSENSA, KSENSB, KSENSC, KSENSD -0.3 3 V Over operating free-air temperature range (unless otherwise noted) 6
Output voltage GATE1-8 -0.3 12 V Over operating free-air temperature range (unless otherwise noted) 6
Voltage SDAI, SDAO, SCL, INT -0.3 4 V Over operating free-air temperature range (unless otherwise noted) 6
Voltage DRAIN1-8 -0.3 70 V Over operating free-air temperature range (unless otherwise noted) 6
Voltage TEST0-3, ATST_DCPL0, DTST_DCPL1 -0.3 4 V Over operating free-air temperature range (unless otherwise noted) 6
Voltage AGND -0.3 0.3 V Over operating free-air temperature range (unless otherwise noted) 6
Sink current INT, SDAO 20 mA Over operating free-air temperature range (unless otherwise noted) 6
Lead temperature 260 °C 1.6 mm (1/16-inch) from case for 10 seconds 6
Storage temperature Tstg -65 150 °C 6
Junction-to-ambient thermal resistance RθJA 25.3 °C/W 7
Junction-to-case (top) thermal resistance RθJC(top) 9.7 °C/W 7
Junction-to-board thermal resistance RθJB 3.7 °C/W 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 0.5 °C/W 7
VPWR current consumption IVPWR 10 12.5 mA VVPWR = 50 V 7
VPWR UVLO falling threshold VUVLOPW_F 14.5 17.5 V 7
VPWR UVLO rising threshold VUVLOPW_R 15.5 18.5 V 7
VPWR undervoltage falling threshold VPUV_F 25 26.5 28 V VPUV threshold 7
VDD current consumption IVDD 6 12 mA 7
VDD UVLO falling threshold VUVDD_F 2.1 2.25 2.4 V For port deassertion 7
VDD UVLO rising threshold VUVDD_R 2.45 2.6 2.75 V 7
VDD UVLO warning threshold VUVW_F 2.6 2.8 3 V 7
Detection current, first detection point IDISC 145 160 190 µA First detection point, VVPWR, VDRAINn = 0 V 7
Detection current, second detection point IDISC 235 270 300 µA Second detection point, VVPWR, VDRAINn = 0 V 7
Detection current, high-current detection point IDISC 490 540 585 µA High-current detection point, VVPWR, VDRAINn = 0 V 7
Open-circuit detection voltage Vdetect 23.5 26 29 V VVPWR, VDRAINn 7
Rejected resistance low range RREJ_LOW 0.86 15 kΩ 7
Rejected resistance high range RREJ_HI 33 100 kΩ 7
Accepted resistance range RACCEPT 19 25 26.5 kΩ 7
Classification voltage VCLASS 15.5 18.5 20.5 V VVPWR, VDRAINn, VSENn ≥ 0 mV, Iport ≥ 180 µA 8
Classification current limit ICLASS_Lim 65 75 90 mA VVPWR, VDRAINn = 0 V 8
Classification threshold current, class 0-1 ICLASS_TH 5 8 mA Class 0-1 8
Classification threshold current, class 1-2 ICLASS_TH 13 16 mA Class 1-2 8
Classification threshold current, class 2-3 ICLASS_TH 21 25 mA Class 2-3 8
Classification threshold current, class 3-4 ICLASS_TH 31 35 mA Class 3-4 8
Classification threshold current, class 4-class overcurrent ICLASS_TH 45 51 mA Class 4-Class overcurrent 8
Mark voltage VMARK 7 10 V 4 mA ≥ Iport ≥ 180 µA, VVPWR, VDRAINn 8
Mark sinking current limit IMARK_Lim 10 70 90 mA VVPWR, VDRAINn = 0 V 8
Gate drive voltage VGOH 10 12.5 V VGATEn , IGATE = -1 µA 8
Gate sinking current with Power-on Reset, OSS detected or port turn off command IGO 60 100 190 mA VGATEn = 5 V 8
Gate sinking current with port short-circuit IGO short 60 100 190 mA VGATEn = 5 V, VSENn ≥ Vshort (or Vshort2X if 2X mode) 8
Gate sourcing current IGO+ 39 50 63 µA VGATEn = 0V 8
Power Good threshold VPGT 1 2.13 3 V Measured at VDRAINn 8
Shorted FET threshold VSHT 4 6 8 V Measured at VDRAINn 8
Resistance from DRAINn to VPWR RDRAIN 80 100 190 kΩ Any operating mode except during detection or while the port is ON, including in device RESET state 8
DRAINn pin bias current IDRAIN 75 120 µA VVPWR, VDRAINn = 30 V, port ON 8
Conversion time, current measurement tCONV 0.64 0.8 0.96 ms All ranges, each port 8
Conversion time, voltage measurement tCONV_V 0.82 1.03 1.2 ms All ranges, each port 8
Integration (averaging) time, current tINT_CUR 82 102 122 ms Each port, port ON current 8
ICUT limit VCUT 9.6 10.2 10.8 mV VDRAINn = 0 V, POL(3:0) = 0001b 9
Ishort threshold in 1X mode and during inrush Vshort 234 306 mV Threshold for GATE to be less than 1 V, 2 µS after application of pulse 9
Shutdown temperature TSD 135 146 °C Temperature rising 9
Sense pin bias current Ibias -2.5 0 µA Port ON or during class 9

CAD (KiCad official)

  • Symbol: TPS2388RTQR
  • Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
  • 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: tps2388rtqr-etched.step / tps2388rtqr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2388rtqr.step / tps2388rtqr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (87 pp, sha256 f972665f18da3b8a, retrieved 2026-10-30, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF