component
TPS2350PWR
Public Made by Adomby adom
Texas Instruments Supervisor And Reset ICs, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1d ago |
| viewers | 1d ago |
| package.json | 1d ago |
| page.json | 1d ago |
| README.md | 1d ago |
| tps2350pwr-etched.glb | 1d ago |
| tps2350pwr-etched.step | 1d ago |
| tps2350pwr-hero.glb | 1d ago |
| tps2350pwr-hero.overlay.json | 1d ago |
| tps2350pwr.glb | 1d ago |
| tps2350pwr.kicad_mod | 1d ago |
| tps2350pwr.kicad_sym | 1d ago |
| tps2350pwr.lbr | 1d ago |
| tps2350pwr.step | 1d ago |
TPS2350PWR
Texas Instruments · Supervisor And Reset ICs · TSSOP-14
TPS2350PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RTN | power_in | Supply return (ground) for the device; for negative-voltage systems it connects directly to the return node of the input power bus, and all voltages are referenced to the more negative of -VINA and -VINB. |
| 2 | FLT | output | Open-drain, active-low fault indication that sinks 10 mA when in fault, withstands 80 V without leakage when not faulted, and withstands transients to 100 V when limited by a series resistor of at least 10 kΩ. |
| 3 | UV | input | Under-voltage comparator input, typically a divider from RTN to SOURCE, which must be more than 1.4 V above SOURCE (with no fault and OV low) to enable the linear current amplifier. |
| 4 | OV | input | Over-voltage comparator input, typically a divider from RTN to SOURCE, which must be less than 1.4 V above SOURCE (with UV high and no fault) to enable the linear current amplifier. |
| 5 | FLTTIM | bidirectional | Fault timer pin where an external capacitor from FLTTIM to SOURCE sets the fault timeout; the capacitor is charged to the 4-V fault threshold and then discharged at about 1% of the charge rate to set the retry duty cycle. |
| 6 | RAMP | bidirectional | Inrush slew-rate programming pin where an external capacitor from RAMP to SOURCE sets turn-on current slew rate; when fully charged RAMP may exceed SOURCE by 6 V, with the reference clamped to 42 mV. |
| 7 | SOURCE | bidirectional | Negative current sense input and common connection to the supply-selector FET sources, which the supply select comparator ties to the more negative of -VINA and -VINB, and to the negative terminal of the sense resistor. |
| 8 | GATB | output | Gate drive for the external N-channel FET that selects -VINB; it is pulled 14 V above -VINB when -VINB is more negative than -VINA and pulled down to -VINA when it is not. |
| 9 | GATA | output | Gate drive for the external N-channel FET that selects -VINA; it is pulled 14 V above -VINA when -VINA is more negative than -VINB and pulled down to -VINB when it is not. |
| 10 | SENSE | input | Positive current sense input, where the linear current amplifier regulates SENSE to 42 mV during ramp-up and a fast overload above 120 mV pulls GAT low, bypassing the fault timer. |
| 11 | GAT | output | Gate drive for the external N-channel protection MOSFET that ramps load current and disconnects on a fault; when fully enhanced the LCA drives GAT 14 V above SOURCE. |
| 12 | PG | output | Open-drain, active-high power-good indication that the power FET is fully enhanced and load current is below the commanded level; it withstands 80 V without leakage when power is not good and sinks 10 mA when in fault. |
| 13 | -VINB | power_in | Negative supply input B that connects directly to the second input supply negative rail; the recommended input supply range is -12 V to -80 V with respect to RTN. |
| 14 | -VINA | power_in | Negative supply input A that connects directly to the first input supply negative rail; the recommended input supply range is -12 V to -80 V with respect to RTN. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
TPS2350PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
tps2350pwr-etched.step/tps2350pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps2350pwr.step/tps2350pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
99780b23bedb684a, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).