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TPS2331IDR

Texas Instruments · Supervisor And Reset ICs · SOIC-14

TPS2331IDR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GATE output Connects to the gate of the external N-channel high-side MOSFET; sources approximately 15 µA when enabled and the charge pump generates 9 V-12 V gate-to-source drive.
2 DGND power_in Digital ground for the controller.
3 TIMER output Capacitor from TIMER to ground sets the circuit-breaker deglitch time; the latch trips at about 0.5 V, and a minimum 50 pF is strongly recommended in high-power or high-temperature applications to prevent false triggering.
4 VREG output Output of the internal low-dropout regulator, less than 5.5 V, for the device; a 0.1 µF ceramic capacitor to ground is recommended for noise rejection.
5 VSENSE input Power-good sense input; PWRGD is pulled low when VSENSE falls below approximately 1.23 V (20 µs deglitch).
6 AGND power_in Analog ground; connect to DGND as close as possible.
7 ISENSE input Current-sense input connected to the MOSFET drain; an overcurrent is assumed when ISENSE is pulled below ISET, and VI(ISENSE) must never exceed VI(IN).
8 IN power_in Input voltage supply (3 V to 13 V) that powers the device and the external MOSFET; the device supports 3 V, 5 V, or 12 V operation and remains disabled until IN is established.
9 AGND power_in Analog ground; connect to DGND as close as possible.
10 ISET input Sets the circuit-breaker threshold through an external resistor to IN, with a 50 µA internal current source; VI(ISET) must never exceed VI(IN).
11 FAULT output Open-drain overcurrent fault output that is pulled low and latches off the device when TIMER reaches 0.5 V.
12 PWRGD output Open-drain power-good output, asserted low when VSENSE is below the approximately 1.23 V reference; it is pulled up to its pullup rail while the device is disabled.
13 ENABLE input Active-high enable on the TPS2331 (active-low on the TPS2330); holding it in the disable state for more than 50 µs discharges the gate and the output bulk capacitance.
14 DISCH output Connects to the source of the external N-channel MOSFET to discharge the load when the MOSFET is disabled, and serves as the reference for internal gate-voltage clamp circuitry.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Power Management (PMIC)
Pins 14

CAD (KiCad official)

  • Symbol: TPS2331IDR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: tps2331idr-etched.step / tps2331idr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps2331idr.step / tps2331idr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (29 pp, sha256 d6a67c69fef8f4da, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF